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| author | Mourad Gouicem <[email protected]> | 2018-02-13 08:46:40 -0800 |
|---|---|---|
| committer | Mourad Gouicem <[email protected]> | 2018-02-13 08:46:40 -0800 |
| commit | bfe2d201e61b6f6c351d8248db4c977ca7c962b7 (patch) | |
| tree | 028820922137f4be81abe1c7d956b4c70c2bbea5 | |
| parent | fd587b55ca8f03f60cc14fa53448c04229dd2629 (diff) | |
| download | xbyak-bfe2d201e61b6f6c351d8248db4c977ca7c962b7.tar.gz xbyak-bfe2d201e61b6f6c351d8248db4c977ca7c962b7.zip | |
Change default value for n_cores in setCacheHierarchy.
If the default value is 0 and the cpu has no leaf B, then in the loop
on the subleaves of leaf 4, the number of cores sharing a data cache will be 0.
| -rw-r--r-- | xbyak/xbyak_util.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/xbyak/xbyak_util.h b/xbyak/xbyak_util.h index 36fe3c0..ca02534 100644 --- a/xbyak/xbyak_util.h +++ b/xbyak/xbyak_util.h @@ -96,7 +96,7 @@ class Cpu { // const unsigned int INSTRUCTION_CACHE = 2; const unsigned int UNIFIED_CACHE = 3; unsigned int smt_width = 0; - unsigned int n_cores = 0; + unsigned int n_cores = (unsigned int) -1; unsigned int data[4]; /* |