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| author | Denis Samoilov <[email protected]> | 2019-03-05 12:37:36 -0800 |
|---|---|---|
| committer | MITSUNARI Shigeo <[email protected]> | 2019-03-06 10:08:37 +0900 |
| commit | d397e824f42f68a60c7986d70d9313a1e92bd49a (patch) | |
| tree | b98382481c817b82936bf6e32a503564db337a36 | |
| parent | a669e092717691953ee5faf322995920c67b998f (diff) | |
| download | xbyak-d397e824f42f68a60c7986d70d9313a1e92bd49a.tar.gz xbyak-d397e824f42f68a60c7986d70d9313a1e92bd49a.zip | |
fix number of cores that share LLC cache
The issue was introduced in 4c262fa66d713b429af59537f0af1eb5f24bc69a.
Extra division by smt_width in setNumCores() leads to incorrect number of cores
which share LLC cache that is determined by setCacheHierarchy()
| -rw-r--r-- | xbyak/xbyak_util.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/xbyak/xbyak_util.h b/xbyak/xbyak_util.h index 78ff065..13f4693 100644 --- a/xbyak/xbyak_util.h +++ b/xbyak/xbyak_util.h @@ -132,9 +132,6 @@ class Cpu { numCores_[level - 1] = extractBit(data[1], 0, 15); } } - if (numCores_[SmtLevel - 1] != 0) { - numCores_[CoreLevel - 1] /= numCores_[SmtLevel - 1]; - } } else { /* Failed to deremine num of cores without x2APIC support. @@ -205,7 +202,9 @@ public: unsigned int getNumCores(IntelCpuTopologyLevel level) { if (level != SmtLevel && level != CoreLevel) throw Error(ERR_BAD_PARAMETER); if (!x2APIC_supported_) throw Error(ERR_X2APIC_IS_NOT_SUPPORTED); - return numCores_[level - 1]; + return (level == CoreLevel) + ? numCores_[level - 1] / numCores_[SmtLevel - 1] + : numCores_[level - 1]; } unsigned int getDataCacheLevels() const { return dataCacheLevels_; } |