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| author | Ryan Houdek <[email protected]> | 2020-10-04 16:16:16 -0700 |
|---|---|---|
| committer | Ryan Houdek <[email protected]> | 2020-10-04 16:21:59 -0700 |
| commit | 99e2b13b212e4e3af53e8c53722ac1be79650b1a (patch) | |
| tree | e987e8085820d25f2cb349686e72aafe7115858d | |
| parent | 0140eeff1fffcf5069dea3abb57095695320971c (diff) | |
| download | xbyak-99e2b13b212e4e3af53e8c53722ac1be79650b1a.tar.gz xbyak-99e2b13b212e4e3af53e8c53722ac1be79650b1a.zip | |
Fixes extended feature support checking
This was locking feature checks between Intel and AMD.
Most of the features overlap between AMD and Intel for extended flag
information in fn8000_0001.
Fixes detection of LZCNT/ABM on my Zen+ CPU
| -rw-r--r-- | xbyak/xbyak_util.h | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/xbyak/xbyak_util.h b/xbyak/xbyak_util.h index 1516fc3..1e9bd1e 100644 --- a/xbyak/xbyak_util.h +++ b/xbyak/xbyak_util.h @@ -389,19 +389,35 @@ public: if (ECX == get32bitAsBE(amd)) { type_ |= tAMD; getCpuid(0x80000001, data); - if (EDX & (1U << 31)) type_ |= t3DN; - if (EDX & (1U << 15)) type_ |= tCMOV; - if (EDX & (1U << 30)) type_ |= tE3DN; - if (EDX & (1U << 22)) type_ |= tMMX2; - if (EDX & (1U << 27)) type_ |= tRDTSCP; + if (EDX & (1U << 31)) { + type_ |= t3DN; + // 3DNow! implies support for PREFETCHW on AMD + type_ |= tPREFETCHW; + } + + if (EDX & (1U << 29)) { + // Long mode implies support for PREFETCHW on AMD + type_ |= tPREFETCHW; + } } if (ECX == get32bitAsBE(intel)) { type_ |= tINTEL; + } + + // Extended flags information + getCpuid(0x80000000, data); + if (EAX >= 0x80000001) { getCpuid(0x80000001, data); + + if (EDX & (1U << 31)) type_ |= t3DN; + if (EDX & (1U << 30)) type_ |= tE3DN; if (EDX & (1U << 27)) type_ |= tRDTSCP; + if (EDX & (1U << 22)) type_ |= tMMX2; + if (EDX & (1U << 15)) type_ |= tCMOV; if (ECX & (1U << 5)) type_ |= tLZCNT; if (ECX & (1U << 8)) type_ |= tPREFETCHW; } + getCpuid(1, data); if (ECX & (1U << 0)) type_ |= tSSE3; if (ECX & (1U << 9)) type_ |= tSSSE3; |