From 208acb30260c6221b7684993cd9a253c4e8b9606 Mon Sep 17 00:00:00 2001
From: Yang Liu <liuyang22@iscas.ac.cn>
Date: Sat, 17 Feb 2024 18:22:24 +0800
Subject: backend/rv64: Implement A32SetCpsrNZCV

---
 src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp b/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
index 7787b4bb..ff9bc462 100644
--- a/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
+++ b/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp
@@ -248,4 +248,14 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx,
     as.SW(Xscratch0, offsetof(A32JitState, cpsr_nzcv), Xstate);
 }
 
+template<>
+void EmitIR<IR::Opcode::A32SetCpsrNZCV>(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst) {
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+
+    auto Xnzcv = ctx.reg_alloc.ReadX(args[0]);
+    RegAlloc::Realize(Xnzcv);
+
+    as.SW(Xnzcv, offsetof(A32JitState, cpsr_nzcv), Xstate);
+}
+
 }  // namespace Dynarmic::Backend::RV64
-- 
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