atsame51: add initial support for feather-m4-can

8 files changed, 276 insertions, 1 deletions

diff --git a/Makefile b/Makefile
index ac6f82715..284e4a959 100644
--- a/Makefile
+++ b/Makefile
@@ -338,6 +338,8 @@ smoketest:
 	@$(MD5SUM) test.hex
 	$(TINYGO) build -size short -o test.hex -target=atsame54-xpro       examples/blinky1
 	@$(MD5SUM) test.hex
+	$(TINYGO) build -size short -o test.hex -target=feather-m4-can      examples/blinky1
+	@$(MD5SUM) test.hex
 	# test pwm
 	$(TINYGO) build -size short -o test.hex -target=itsybitsy-m0        examples/pwm
 	@$(MD5SUM) test.hex
diff --git a/README.md b/README.md
index 40643fc5f..aa61e1c45 100644
--- a/README.md
+++ b/README.md
@@ -43,13 +43,14 @@ See the [getting started instructions](https://tinygo.org/getting-started/) for
 
 You can compile TinyGo programs for microcontrollers, WebAssembly and Linux.
 
-The following 56 microcontroller boards are currently supported:
+The following 57 microcontroller boards are currently supported:
 
 * [Adafruit Circuit Playground Bluefruit](https://www.adafruit.com/product/4333)
 * [Adafruit Circuit Playground Express](https://www.adafruit.com/product/3333)
 * [Adafruit CLUE](https://www.adafruit.com/product/4500)
 * [Adafruit Feather M0](https://www.adafruit.com/product/2772)
 * [Adafruit Feather M4](https://www.adafruit.com/product/3857)
+* [Adafruit Feather M4 CAN](https://www.adafruit.com/product/4759)
 * [Adafruit Feather nRF52840 Express](https://www.adafruit.com/product/4062)
 * [Adafruit Feather STM32F405 Express](https://www.adafruit.com/product/4382)
 * [Adafruit ItsyBitsy M0](https://www.adafruit.com/product/3727)
diff --git a/src/machine/board_feather-m4-can.go b/src/machine/board_feather-m4-can.go
new file mode 100644
index 000000000..536e4b62e
--- /dev/null
+++ b/src/machine/board_feather-m4-can.go
@@ -0,0 +1,142 @@
+// +build feather_m4_can
+
+package machine
+
+import (
+	"device/sam"
+	"runtime/interrupt"
+)
+
+// used to reset into bootloader
+const RESET_MAGIC_VALUE = 0xf01669ef
+
+// GPIO Pins
+const (
+	D0  = PB17 // UART0 RX/PWM available
+	D1  = PB16 // UART0 TX/PWM available
+	D4  = PA14 // PWM available
+	D5  = PA16 // PWM available
+	D6  = PA18 // PWM available
+	D7  = PB03 // neopixel power
+	D8  = PB02 // built-in neopixel
+	D9  = PA19 // PWM available
+	D10 = PA20 // can be used for PWM or UART1 TX
+	D11 = PA21 // can be used for PWM or UART1 RX
+	D12 = PA22 // PWM available
+	D13 = PA23 // PWM available
+	D21 = PA13 // PWM available
+	D22 = PA12 // PWM available
+	D23 = PB22 // PWM available
+	D24 = PB23 // PWM available
+	D25 = PA17 // PWM available
+)
+
+// Analog pins
+const (
+	A0 = PA02 // ADC/AIN[0]
+	A1 = PA05 // ADC/AIN[2]
+	A2 = PB08 // ADC/AIN[3]
+	A3 = PB09 // ADC/AIN[4]
+	A4 = PA04 // ADC/AIN[5]
+	A5 = PA06 // ADC/AIN[10]
+)
+
+const (
+	LED       = D13
+	NEOPIXELS = D8
+)
+
+// UART0 aka USBCDC pins
+const (
+	USBCDC_DM_PIN = PA24
+	USBCDC_DP_PIN = PA25
+)
+
+const (
+	UART_TX_PIN = D1
+	UART_RX_PIN = D0
+)
+
+const (
+	UART2_TX_PIN = A4
+	UART2_RX_PIN = A5
+)
+
+// I2C pins
+const (
+	SDA_PIN = D22 // SDA: SERCOM2/PAD[0]
+	SCL_PIN = D21 // SCL: SERCOM2/PAD[1]
+)
+
+// SPI pins
+const (
+	SPI0_SCK_PIN = D25 // SCK: SERCOM1/PAD[1]
+	SPI0_SDO_PIN = D24 // SDO: SERCOM1/PAD[3]
+	SPI0_SDI_PIN = D23 // SDI: SERCOM1/PAD[2]
+)
+
+// CAN pins
+const (
+	CAN0_TX = PA22
+	CAN0_RX = PA23
+
+	CAN1_STANDBY = PB12
+	CAN1_TX      = PB14
+	CAN1_RX      = PB15
+	BOOST_EN     = PB13 // power control of CAN1's TCAN1051HGV (H: enable)
+
+	CAN_STANDBY = CAN1_STANDBY
+	CAN_S       = CAN1_STANDBY
+	CAN_TX      = CAN1_TX
+	CAN_RX      = CAN1_RX
+)
+
+// USB CDC identifiers
+const (
+	usb_STRING_PRODUCT      = "Adafruit Feather M4 CAN"
+	usb_STRING_MANUFACTURER = "Adafruit"
+)
+
+var (
+	usb_VID uint16 = 0x239A
+	usb_PID uint16 = 0x80CD
+)
+
+var (
+	UART1 = UART{
+		Buffer: NewRingBuffer(),
+		Bus:    sam.SERCOM5_USART_INT,
+		SERCOM: 5,
+	}
+
+	UART2 = UART{
+		Buffer: NewRingBuffer(),
+		Bus:    sam.SERCOM0_USART_INT,
+		SERCOM: 0,
+	}
+)
+
+func init() {
+	UART1.Interrupt = interrupt.New(sam.IRQ_SERCOM5_2, UART1.handleInterrupt)
+	UART2.Interrupt = interrupt.New(sam.IRQ_SERCOM0_2, UART2.handleInterrupt)
+
+	// turn on neopixel
+	D7.Configure(PinConfig{Mode: PinOutput})
+	D7.High()
+}
+
+// I2C on the Feather M4.
+var (
+	I2C0 = &I2C{
+		Bus:    sam.SERCOM2_I2CM,
+		SERCOM: 2,
+	}
+)
+
+// SPI on the Feather M4.
+var (
+	SPI0 = SPI{
+		Bus:    sam.SERCOM1_SPIM,
+		SERCOM: 1,
+	}
+)
diff --git a/src/machine/machine_atsame51j19.go b/src/machine/machine_atsame51j19.go
new file mode 100644
index 000000000..4a2021bd1
--- /dev/null
+++ b/src/machine/machine_atsame51j19.go
@@ -0,0 +1,59 @@
+// +build sam,atsame51,atsame51j19
+
+// Peripheral abstraction layer for the atsame51.
+//
+// Datasheet:
+// http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf
+//
+package machine
+
+import "device/sam"
+
+const HSRAM_SIZE = 0x00030000
+
+// This chip has five TCC peripherals, which have PWM as one feature.
+var (
+	TCC0 = (*TCC)(sam.TCC0)
+	TCC1 = (*TCC)(sam.TCC1)
+	TCC2 = (*TCC)(sam.TCC2)
+	TCC3 = (*TCC)(sam.TCC3)
+	TCC4 = (*TCC)(sam.TCC4)
+)
+
+func (tcc *TCC) configureClock() {
+	// Turn on timer clocks used for the TCC and use generic clock generator 0.
+	switch tcc.timer() {
+	case sam.TCC0:
+		sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_)
+		sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
+	case sam.TCC1:
+		sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_)
+		sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
+	case sam.TCC2:
+		sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_)
+		sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
+	case sam.TCC3:
+		sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC3_)
+		sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC3].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
+	case sam.TCC4:
+		sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_TCC4_)
+		sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
+	}
+}
+
+func (tcc *TCC) timerNum() uint8 {
+	switch tcc.timer() {
+	case sam.TCC0:
+		return 0
+	case sam.TCC1:
+		return 1
+	case sam.TCC2:
+		return 2
+	case sam.TCC3:
+		return 3
+	case sam.TCC4:
+		return 4
+	default:
+		return 0x0f // should not happen
+	}
+}
diff --git a/src/runtime/runtime_atsame51j19.go b/src/runtime/runtime_atsame51j19.go
new file mode 100644
index 000000000..76dce7332
--- /dev/null
+++ b/src/runtime/runtime_atsame51j19.go
@@ -0,0 +1,43 @@
+// +build sam,atsame51,atsame51j19
+
+package runtime
+
+import (
+	"device/sam"
+)
+
+func initSERCOMClocks() {
+	// Turn on clock to SERCOM0 for UART0
+	sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_)
+	sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+		sam.GCLK_PCHCTRL_CHEN)
+
+	// sets the "slow" clock shared by all SERCOM
+	sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOMX_SLOW].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+		sam.GCLK_PCHCTRL_CHEN)
+
+	// Turn on clock to SERCOM1
+	sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_)
+	sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+		sam.GCLK_PCHCTRL_CHEN)
+
+	// Turn on clock to SERCOM2
+	sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_)
+	sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+		sam.GCLK_PCHCTRL_CHEN)
+
+	// Turn on clock to SERCOM3
+	sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_)
+	sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+		sam.GCLK_PCHCTRL_CHEN)
+
+	// Turn on clock to SERCOM4
+	sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_)
+	sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+		sam.GCLK_PCHCTRL_CHEN)
+
+	// Turn on clock to SERCOM5
+	sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_)
+	sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+		sam.GCLK_PCHCTRL_CHEN)
+}
diff --git a/targets/atsame51j19a.json b/targets/atsame51j19a.json
new file mode 100644
index 000000000..98136769d
--- /dev/null
+++ b/targets/atsame51j19a.json
@@ -0,0 +1,10 @@
+{
+	"inherits": ["cortex-m4"],
+	"build-tags": ["atsame51j19a", "atsame51j19", "atsame51", "atsame5x", "sam"],
+	"linkerscript": "targets/atsame5xx19.ld",
+	"extra-files": [
+		"src/device/sam/atsame51j19a.s"
+	],
+	"openocd-transport": "swd",
+	"openocd-target": "atsame5x"
+}
diff --git a/targets/atsame5xx19.ld b/targets/atsame5xx19.ld
new file mode 100644
index 000000000..908ce6a84
--- /dev/null
+++ b/targets/atsame5xx19.ld
@@ -0,0 +1,10 @@
+
+MEMORY
+{
+    FLASH_TEXT (rw) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x00080000-0x4000  /* First 16KB used by bootloader */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x00030000
+}
+
+_stack_size = 4K;
+
+INCLUDE "targets/arm.ld"
diff --git a/targets/feather-m4-can.json b/targets/feather-m4-can.json
new file mode 100644
index 000000000..0480eb8f0
--- /dev/null
+++ b/targets/feather-m4-can.json
@@ -0,0 +1,8 @@
+{
+    "inherits": ["atsame51j19a"],
+    "build-tags": ["feather_m4_can"],
+    "flash-1200-bps-reset": "true",
+    "flash-method": "msd",
+    "msd-volume-name": "FTHRCANBOOT",
+    "msd-firmware-name": "firmware.uf2"
+}