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| author | Damian Gryski <[email protected]> | 2021-09-07 20:17:58 -0700 |
|---|---|---|
| committer | Ron Evans <[email protected]> | 2021-09-09 17:51:46 +0200 |
| commit | da6c14481f62986f14bf79009e811f0856b7ca48 (patch) | |
| tree | 6b1396a1793a1b73ea4c8e1a992e6c913641bbd9 | |
| parent | fb5516604d83fb19374e572a8cf3a4721b44412d (diff) | |
| download | tinygo-da6c14481f62986f14bf79009e811f0856b7ca48.tar.gz tinygo-da6c14481f62986f14bf79009e811f0856b7ca48.zip | |
runtime: fix a suspicious bitwise operation
The `0 << nxp.SIM_CLKDIV1_OUTDIV1_Pos` term was duplicated.
No effect other than triggering a static analysis check.
| -rw-r--r-- | src/runtime/runtime_nxpmk66f18.go | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/runtime/runtime_nxpmk66f18.go b/src/runtime/runtime_nxpmk66f18.go index d31ff0d05..ab985661a 100644 --- a/src/runtime/runtime_nxpmk66f18.go +++ b/src/runtime/runtime_nxpmk66f18.go @@ -140,7 +140,7 @@ func initSystem() { // now program the clock dividers // config divisors: 180 MHz core, 60 MHz bus, 25.7 MHz flash, USB = IRC48M - nxp.SIM.CLKDIV1.Set((0 << nxp.SIM_CLKDIV1_OUTDIV1_Pos) | (2 << nxp.SIM_CLKDIV1_OUTDIV2_Pos) | (0 << nxp.SIM_CLKDIV1_OUTDIV1_Pos) | (6 << nxp.SIM_CLKDIV1_OUTDIV4_Pos)) + nxp.SIM.CLKDIV1.Set((0 << nxp.SIM_CLKDIV1_OUTDIV1_Pos) | (2 << nxp.SIM_CLKDIV1_OUTDIV2_Pos) | (0 << nxp.SIM_CLKDIV1_OUTDIV3_Pos) | (6 << nxp.SIM_CLKDIV1_OUTDIV4_Pos)) nxp.SIM.CLKDIV2.Set((0 << nxp.SIM_CLKDIV2_USBDIV_Pos)) // switch to PLL as clock source, FLL input = 16 MHz / 512 |