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| author | Matthew Hiles <[email protected]> | 2024-07-11 09:44:43 -0400 |
|---|---|---|
| committer | Ron Evans <[email protected]> | 2024-07-20 18:36:59 +0200 |
| commit | 4af3f618f83e1b881fa72ee480a01ce3e76d7506 (patch) | |
| tree | 6f53ef1819e4d7361247196373cfb94dde627630 | |
| parent | 89340f82dc65ec6b1adec75efec2dafe78368a40 (diff) | |
| download | tinygo-4af3f618f83e1b881fa72ee480a01ce3e76d7506.tar.gz tinygo-4af3f618f83e1b881fa72ee480a01ce3e76d7506.zip | |
rewrite Reply() to fix sending long replies in I2C Target Mode
| -rw-r--r-- | src/machine/machine_rp2040_i2c.go | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/machine/machine_rp2040_i2c.go b/src/machine/machine_rp2040_i2c.go index 1b66a8687..7ca2a87cf 100644 --- a/src/machine/machine_rp2040_i2c.go +++ b/src/machine/machine_rp2040_i2c.go @@ -501,15 +501,23 @@ func (i2c *I2C) Reply(buf []byte) error { } for txPtr < len(buf) { - if stat&rp.I2C0_IC_INTR_MASK_M_TX_EMPTY != 0 { - i2c.Bus.IC_DATA_CMD.Set(uint32(buf[txPtr])) + if i2c.Bus.GetIC_RAW_INTR_STAT_TX_EMPTY() != 0 { + i2c.Bus.SetIC_DATA_CMD_DAT(uint32(buf[txPtr])) txPtr++ + // The DW_apb_i2c flushes/resets/empties the + // TX_FIFO and RX_FIFO whenever there is a transmit abort + // caused by any of the events tracked by the + // IC_TX_ABRT_SOURCE register. + // In other words, it's safe to block until TX FIFO is + // EMPTY--it will empty from being transmitted or on error. + for i2c.Bus.GetIC_RAW_INTR_STAT_TX_EMPTY() == 0 { + } } // This Tx abort is a normal case - we're sending more // data than controller wants to receive - if stat&rp.I2C0_IC_INTR_MASK_M_TX_ABRT != 0 { - i2c.Bus.IC_CLR_TX_ABRT.Get() + if i2c.Bus.GetIC_RAW_INTR_STAT_TX_ABRT() != 0 { + i2c.Bus.GetIC_CLR_TX_ABRT_CLR_TX_ABRT() return nil } |