maixbit: changes according to feedback

7 files changed, 31 insertions, 40 deletions

diff --git a/Makefile b/Makefile
index b506679ed..5a1fd02c4 100644
--- a/Makefile
+++ b/Makefile
@@ -327,10 +327,10 @@ ifneq ($(AVR), 0)
 endif
 	$(TINYGO) build -size short -o test.hex -target=hifive1b            examples/blinky1
 	@$(MD5SUM) test.hex
-	$(TINYGO) build             -o wasm.wasm -target=wasm               examples/wasm/export
-	$(TINYGO) build             -o wasm.wasm -target=wasm               examples/wasm/main
 	$(TINYGO) build -size short -o test.hex -target=maixbit             examples/blinky1
 	@$(MD5SUM) test.hex
+	$(TINYGO) build             -o wasm.wasm -target=wasm               examples/wasm/export
+	$(TINYGO) build             -o wasm.wasm -target=wasm               examples/wasm/main
 
 wasmtest:
 	$(GO) test ./tests/wasm
diff --git a/src/device/riscv/handleinterrupt.S b/src/device/riscv/handleinterrupt.S
index dbf54f01a..c206c0159 100644
--- a/src/device/riscv/handleinterrupt.S
+++ b/src/device/riscv/handleinterrupt.S
@@ -1,4 +1,4 @@
-#ifdef F_EXTENSION
+#ifdef __riscv_flen
 #define NREG 48
 #define LFREG flw
 #define SFREG fsw
@@ -6,7 +6,7 @@
 #define NREG 16
 #endif
 
-#ifdef RV64
+#if __riscv_xlen==64
 #define REGSIZE 8
 #define SREG sd
 #define LREG ld
@@ -41,7 +41,7 @@ handleInterruptASM:
     SREG    t4, 13*REGSIZE(sp)
     SREG    t5, 14*REGSIZE(sp)
     SREG    t6, 15*REGSIZE(sp)
-#ifdef F_EXTENSION
+#ifdef __riscv_flen
     SFREG   f0, (0  + 16)*REGSIZE(sp)
     SFREG   f1, (1  + 16)*REGSIZE(sp)
     SFREG   f2, (2  + 16)*REGSIZE(sp)
@@ -76,7 +76,7 @@ handleInterruptASM:
     SFREG   f31,(31 + 16)*REGSIZE(sp)
 #endif
     call    handleInterrupt
-#ifdef F_EXTENSION
+#ifdef __riscv_flen
     LFREG   f0, (31 + 16)*REGSIZE(sp)
     LFREG   f1, (30 + 16)*REGSIZE(sp)
     LFREG   f2, (29 + 16)*REGSIZE(sp)
diff --git a/src/machine/machine_k210.go b/src/machine/machine_k210.go
index eea477f21..caa1592ba 100644
--- a/src/machine/machine_k210.go
+++ b/src/machine/machine_k210.go
@@ -4,6 +4,7 @@ package machine
 
 import (
 	"device/kendryte"
+	"device/riscv"
 	"errors"
 	"runtime/interrupt"
 )
@@ -33,11 +34,9 @@ const (
 
 // GPIOHS pin interrupt events.
 const (
-	PinRising PinChange = iota + 1
+	PinRising PinChange = 1 << iota
 	PinFalling
-	PinToggle
-	PinHigh
-	PinLow = 8
+	PinToggle = PinRising | PinFalling
 )
 
 var (
@@ -224,12 +223,6 @@ func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error {
 	if change&PinFalling != 0 {
 		kendryte.GPIOHS.FALL_IE.SetBits(1 << gpioPin)
 	}
-	if change&PinHigh != 0 {
-		kendryte.GPIOHS.HIGH_IE.SetBits(1 << gpioPin)
-	}
-	if change&PinLow != 0 {
-		kendryte.GPIOHS.LOW_IE.SetBits(1 << gpioPin)
-	}
 
 	handleInterrupt := func(inter interrupt.Interrupt) {
 
@@ -237,28 +230,28 @@ func (p Pin) SetInterrupt(change PinChange, callback func(Pin)) error {
 
 		if kendryte.GPIOHS.RISE_IE.HasBits(1 << pin) {
 			kendryte.GPIOHS.RISE_IE.ClearBits(1 << pin)
-			kendryte.GPIOHS.RISE_IP.SetBits(1 << pin)
+			// Acknowledge interrupt atomically.
+			riscv.AsmFull(
+				"amoor.w {}, {mask}, {reg}",
+				map[string]interface{}{
+					"mask": uint32(1 << pin),
+					"reg":  &kendryte.GPIOHS.RISE_IP.Reg,
+				})
 			kendryte.GPIOHS.RISE_IE.SetBits(1 << pin)
 		}
 
 		if kendryte.GPIOHS.FALL_IE.HasBits(1 << pin) {
 			kendryte.GPIOHS.FALL_IE.ClearBits(1 << pin)
-			kendryte.GPIOHS.FALL_IP.SetBits(1 << pin)
+			// Acknowledge interrupt atomically.
+			riscv.AsmFull(
+				"amoor.w {}, {mask}, {reg}",
+				map[string]interface{}{
+					"mask": uint32(1 << pin),
+					"reg":  &kendryte.GPIOHS.FALL_IP.Reg,
+				})
 			kendryte.GPIOHS.FALL_IE.SetBits(1 << pin)
 		}
 
-		if kendryte.GPIOHS.HIGH_IE.HasBits(1 << pin) {
-			kendryte.GPIOHS.HIGH_IE.ClearBits(1 << pin)
-			kendryte.GPIOHS.HIGH_IP.SetBits(1 << pin)
-			kendryte.GPIOHS.HIGH_IE.SetBits(1 << pin)
-		}
-
-		if kendryte.GPIOHS.LOW_IE.HasBits(1 << pin) {
-			kendryte.GPIOHS.LOW_IE.ClearBits(1 << pin)
-			kendryte.GPIOHS.LOW_IP.SetBits(1 << pin)
-			kendryte.GPIOHS.LOW_IE.SetBits(1 << pin)
-		}
-
 		pinCallbacks[pin](Pin(pin))
 	}
 
diff --git a/src/runtime/scheduler_tinygoriscv.S b/src/runtime/scheduler_tinygoriscv.S
index 9749ca221..e0aeada5d 100644
--- a/src/runtime/scheduler_tinygoriscv.S
+++ b/src/runtime/scheduler_tinygoriscv.S
@@ -1,4 +1,4 @@
-#ifdef RV64
+#if __riscv_xlen==64
 #define REGSIZE 8
 #define SREG sd
 #define LREG ld
diff --git a/targets/k210.json b/targets/k210.json
index 77fcc53d6..5ddd9dbab 100644
--- a/targets/k210.json
+++ b/targets/k210.json
@@ -1,6 +1,5 @@
 {
 	"inherits": ["riscv64"],
 	"features": ["+a", "+c", "+m", "+f", "+d"],
-	"build-tags": ["k210", "kendryte"],
-	"cflags": ["-D=F_EXTENSION"]
+	"build-tags": ["k210", "kendryte"]
 }
diff --git a/targets/riscv.ld b/targets/riscv.ld
index 6ebee2728..2b9f50276 100644
--- a/targets/riscv.ld
+++ b/targets/riscv.ld
@@ -18,7 +18,7 @@ SECTIONS
      * See: http://blog.japaric.io/stack-overflow-protection/ */
     .stack (NOLOAD) :
     {
-        . = ALIGN(8);
+        . = ALIGN(16);
         . += _stack_size;
         _stack_top = .;
     } >RAM
@@ -29,25 +29,25 @@ SECTIONS
     /* Globals with initial value */
     .data :
     {
-        . = ALIGN(8);
+        . = ALIGN(4);
         /* see https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register */
         PROVIDE( __global_pointer$ = . + (4K / 2) );
         _sdata = .;        /* used by startup code */
         *(.sdata)
         *(.data .data.*)
-        . = ALIGN(8);
+        . = ALIGN(4);
         _edata = .;        /* used by startup code */
     } >RAM AT>FLASH_TEXT
 
     /* Zero-initialized globals  */
     .bss :
     {
-        . = ALIGN(8);
+        . = ALIGN(4);
         _sbss = .;         /* used by startup code */
         *(.sbss)
         *(.bss .bss.*)
         *(COMMON)
-        . = ALIGN(8);
+        . = ALIGN(4);
         _ebss = .;         /* used by startup code */
     } >RAM
 
diff --git a/targets/riscv64.json b/targets/riscv64.json
index f73700c9c..a2a0641f9 100644
--- a/targets/riscv64.json
+++ b/targets/riscv64.json
@@ -5,8 +5,7 @@
 	"cflags": [
 		"--target=riscv64--none",
 		"-march=rv64gc",
-		"-mabi=lp64",
-		"-D=RV64"
+		"-mabi=lp64"
 	],
 	"ldflags": [
 		"-melf64lriscv"