diff options
| author | Ayke van Laethem <[email protected]> | 2022-04-20 14:19:06 +0200 |
|---|---|---|
| committer | Ron Evans <[email protected]> | 2022-04-21 15:18:18 +0200 |
| commit | 52233790ccd6fc4f8a9b3edeeaa90b5d7ec03f6b (patch) | |
| tree | 32fcd8b64210267278a27cd637435d9558874294 /src/device | |
| parent | 9160f3f16dfd39011054dac2423679a90777f172 (diff) | |
| download | tinygo-52233790ccd6fc4f8a9b3edeeaa90b5d7ec03f6b.tar.gz tinygo-52233790ccd6fc4f8a9b3edeeaa90b5d7ec03f6b.zip | |
mimxrt1062: simplify arm.AsmFull to arm.Asm
This means fewer instances of arm.AsmFull, which I'd like to remove
eventually if possible.
Diffstat (limited to 'src/device')
| -rw-r--r-- | src/device/nxp/mimxrt1062_mpu.go | 68 |
1 files changed, 21 insertions, 47 deletions
diff --git a/src/device/nxp/mimxrt1062_mpu.go b/src/device/nxp/mimxrt1062_mpu.go index f69dfc3fa..9f3b5a20d 100644 --- a/src/device/nxp/mimxrt1062_mpu.go +++ b/src/device/nxp/mimxrt1062_mpu.go @@ -142,18 +142,14 @@ func (mpu *MPU_Type) Enable(enable bool) { if enable { mpu.CTRL.Set(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk) SystemControl.SHCSR.SetBits(SCB_SHCSR_MEMFAULTENA_Msk) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) + arm.Asm("dsb 0xF") + arm.Asm("isb 0xF") enableDcache(true) enableIcache(true) } else { enableIcache(false) enableDcache(false) - arm.AsmFull(` - dmb 0xF - `, nil) + arm.Asm("dmb 0xF") SystemControl.SHCSR.ClearBits(SCB_SHCSR_MEMFAULTENA_Msk) mpu.CTRL.ClearBits(MPU_CTRL_ENABLE_Msk) } @@ -188,31 +184,21 @@ func (mpu *MPU_Type) SetRASR(size RegionSize, access AccessPerms, ext Extension, func enableIcache(enable bool) { if enable != SystemControl.CCR.HasBits(SCB_CCR_IC_Msk) { if enable { - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) + arm.Asm("dsb 0xF") + arm.Asm("isb 0xF") SystemControl.ICIALLU.Set(0) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) + arm.Asm("dsb 0xF") + arm.Asm("isb 0xF") SystemControl.CCR.SetBits(SCB_CCR_IC_Msk) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) + arm.Asm("dsb 0xF") + arm.Asm("isb 0xF") } else { - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) + arm.Asm("dsb 0xF") + arm.Asm("isb 0xF") SystemControl.CCR.ClearBits(SCB_CCR_IC_Msk) SystemControl.ICIALLU.Set(0) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) + arm.Asm("dsb 0xF") + arm.Asm("isb 0xF") } } } @@ -227,9 +213,7 @@ func enableDcache(enable bool) { if enable != SystemControl.CCR.HasBits(SCB_CCR_DC_Msk) { if enable { SystemControl.CSSELR.Set(0) - arm.AsmFull(` - dsb 0xF - `, nil) + arm.Asm("dsb 0xF") ccsidr := SystemControl.CCSIDR.Get() sets := (ccsidr & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos for sets != 0 { @@ -242,23 +226,15 @@ func enableDcache(enable bool) { } sets-- } - arm.AsmFull(` - dsb 0xF - `, nil) + arm.Asm("dsb 0xF") SystemControl.CCR.SetBits(SCB_CCR_DC_Msk) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) + arm.Asm("dsb 0xF") + arm.Asm("isb 0xF") } else { SystemControl.CSSELR.Set(0) - arm.AsmFull(` - dsb 0xF - `, nil) + arm.Asm("dsb 0xF") SystemControl.CCR.ClearBits(SCB_CCR_DC_Msk) - arm.AsmFull(` - dsb 0xF - `, nil) + arm.Asm("dsb 0xF") dcacheCcsidr.Set(SystemControl.CCSIDR.Get()) dcacheSets.Set((dcacheCcsidr.Get() & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos) for dcacheSets.Get() != 0 { @@ -271,10 +247,8 @@ func enableDcache(enable bool) { } dcacheSets.Set(dcacheSets.Get() - 1) } - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) + arm.Asm("dsb 0xF") + arm.Asm("isb 0xF") } } } |