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authorAyke van Laethem <[email protected]>2019-03-30 12:54:36 +0100
committerRon Evans <[email protected]>2019-07-07 14:03:24 +0200
commitffa38b183b32331dd247e337a985c4eb5a7d9350 (patch)
tree2f858af25739909e2da7f6b0b3e59eacc5071d41 /targets
parentf0eb4eef5a842be56288590ef3ba8766432c67ac (diff)
downloadtinygo-ffa38b183b32331dd247e337a985c4eb5a7d9350.tar.gz
tinygo-ffa38b183b32331dd247e337a985c4eb5a7d9350.zip
all: add HiFive1 rev B board with RISC-V architecture
This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
Diffstat (limited to 'targets')
-rw-r--r--targets/fe310.json5
-rw-r--r--targets/hifive1b.json7
-rw-r--r--targets/hifive1b.ld10
-rw-r--r--targets/riscv.json25
-rw-r--r--targets/riscv.ld56
5 files changed, 103 insertions, 0 deletions
diff --git a/targets/fe310.json b/targets/fe310.json
new file mode 100644
index 000000000..36bb7452d
--- /dev/null
+++ b/targets/fe310.json
@@ -0,0 +1,5 @@
+{
+ "inherits": ["riscv"],
+ "features": ["+a", "+c", "+m"],
+ "build-tags": ["fe310", "sifive"]
+}
diff --git a/targets/hifive1b.json b/targets/hifive1b.json
new file mode 100644
index 000000000..9161c77b8
--- /dev/null
+++ b/targets/hifive1b.json
@@ -0,0 +1,7 @@
+{
+ "inherits": ["fe310"],
+ "build-tags": ["hifive1b"],
+ "ldflags": [
+ "-T", "targets/hifive1b.ld"
+ ]
+}
diff --git a/targets/hifive1b.ld b/targets/hifive1b.ld
new file mode 100644
index 000000000..29ec78ad5
--- /dev/null
+++ b/targets/hifive1b.ld
@@ -0,0 +1,10 @@
+
+MEMORY
+{
+ FLASH_TEXT (rw) : ORIGIN = 0x20010000, LENGTH = 0x6a120
+ RAM (xrw) : ORIGIN = 0x80000000, LENGTH = 0x4000
+}
+
+_stack_size = 2K;
+
+INCLUDE "targets/riscv.ld"
diff --git a/targets/riscv.json b/targets/riscv.json
new file mode 100644
index 000000000..581c5e8ce
--- /dev/null
+++ b/targets/riscv.json
@@ -0,0 +1,25 @@
+{
+ "llvm-target": "riscv32--none",
+ "goos": "linux",
+ "goarch": "arm",
+ "build-tags": ["tinygo.riscv", "linux", "arm"],
+ "gc": "conservative",
+ "compiler": "riscv64-unknown-elf-gcc",
+ "linker": "riscv64-unknown-elf-ld",
+ "cflags": [
+ "-march=rv32imac",
+ "-mabi=ilp32",
+ "-Os",
+ "-Werror",
+ "-nostdinc",
+ "-fno-exceptions", "-fno-unwind-tables",
+ "-ffunction-sections", "-fdata-sections"
+ ],
+ "ldflags": [
+ "-melf32lriscv",
+ "--gc-sections"
+ ],
+ "extra-files": [
+ "src/device/riscv/start.S"
+ ]
+}
diff --git a/targets/riscv.ld b/targets/riscv.ld
new file mode 100644
index 000000000..857d2ee48
--- /dev/null
+++ b/targets/riscv.ld
@@ -0,0 +1,56 @@
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.init))
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata.*)
+ . = ALIGN(4);
+ } >FLASH_TEXT
+
+ /* Put the stack at the bottom of RAM, so that the application will
+ * crash on stack overflow instead of silently corrupting memory.
+ * See: http://blog.japaric.io/stack-overflow-protection/ */
+ .stack :
+ {
+ . = ALIGN(4);
+ . += _stack_size;
+ _stack_top = .;
+ } >RAM
+
+ /* Start address (in flash) of .data, used by startup code. */
+ _sidata = LOADADDR(.data);
+
+ /* Globals with initial value */
+ .data :
+ {
+ . = ALIGN(4);
+ /* see https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register */
+ PROVIDE( __global_pointer$ = . + (4K / 2) );
+ _sdata = .; /* used by startup code */
+ *(.data)
+ *(.data*)
+ . = ALIGN(4);
+ _edata = .; /* used by startup code */
+ } >RAM AT>FLASH_TEXT
+
+ /* Zero-initialized globals */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .; /* used by startup code */
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .; /* used by startup code */
+ } >RAM
+}
+
+/* For the memory allocator. */
+_heap_start = _ebss;
+_heap_end = ORIGIN(RAM) + LENGTH(RAM);
+_globals_start = _sdata;
+_globals_end = _ebss;