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Diffstat (limited to 'src/runtime/runtime_atsame51j19.go')
-rw-r--r--src/runtime/runtime_atsame51j19.go43
1 files changed, 43 insertions, 0 deletions
diff --git a/src/runtime/runtime_atsame51j19.go b/src/runtime/runtime_atsame51j19.go
new file mode 100644
index 000000000..76dce7332
--- /dev/null
+++ b/src/runtime/runtime_atsame51j19.go
@@ -0,0 +1,43 @@
+// +build sam,atsame51,atsame51j19
+
+package runtime
+
+import (
+ "device/sam"
+)
+
+func initSERCOMClocks() {
+ // Turn on clock to SERCOM0 for UART0
+ sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_)
+ sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+ sam.GCLK_PCHCTRL_CHEN)
+
+ // sets the "slow" clock shared by all SERCOM
+ sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOMX_SLOW].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+ sam.GCLK_PCHCTRL_CHEN)
+
+ // Turn on clock to SERCOM1
+ sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_)
+ sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+ sam.GCLK_PCHCTRL_CHEN)
+
+ // Turn on clock to SERCOM2
+ sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_)
+ sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+ sam.GCLK_PCHCTRL_CHEN)
+
+ // Turn on clock to SERCOM3
+ sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_)
+ sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+ sam.GCLK_PCHCTRL_CHEN)
+
+ // Turn on clock to SERCOM4
+ sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_)
+ sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+ sam.GCLK_PCHCTRL_CHEN)
+
+ // Turn on clock to SERCOM5
+ sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_)
+ sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
+ sam.GCLK_PCHCTRL_CHEN)
+}