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authorAndrzej Janik <[email protected]>2020-09-02 20:58:54 +0200
committerAndrzej Janik <[email protected]>2020-09-02 20:58:54 +0200
commitefd83981b8d4d26f25389db933bf70756f060f37 (patch)
tree4372b578c6fa511dd3a7f441bca6e451f2e2bc67
parent87cc72494ec492d60011933b76d74d8a82d9393b (diff)
downloadZLUDA-efd83981b8d4d26f25389db933bf70756f060f37.tar.gz
ZLUDA-efd83981b8d4d26f25389db933bf70756f060f37.zip
Add support for blocks
Diffstat
-rw-r--r--ptx/src/test/_Z9vectorAddPKfS0_Pfi.ptx10423
-rw-r--r--ptx/src/test/spirv_run/block.ptx26
-rw-r--r--ptx/src/test/spirv_run/block.spvtxt44
-rw-r--r--ptx/src/test/spirv_run/mod.rs1
-rw-r--r--ptx/src/translate.rs40
5 files changed, 10527 insertions, 7 deletions
diff --git a/ptx/src/test/_Z9vectorAddPKfS0_Pfi.ptx b/ptx/src/test/_Z9vectorAddPKfS0_Pfi.ptx
new file mode 100644
index 0000000..e5bc3d1
--- /dev/null
+++ b/ptx/src/test/_Z9vectorAddPKfS0_Pfi.ptx
@@ -0,0 +1,10423 @@
+
+
+
+
+
+
+
+
+.version 7.0
+.target sm_80, debug
+.address_size 64
+
+
+.func (.param .b32 func_retval0) fabsf
+(
+.param .b32 fabsf_param_0
+)
+;
+
+.weak .func (.param .b32 func_retval0) cudaMalloc(
+.param .b64 cudaMalloc_param_0,
+.param .b64 cudaMalloc_param_1
+)
+{
+.local .align 8 .b8 __local_depot0[8];
+.reg .b64 %SP;
+.reg .b64 %SPL;
+.reg .b32 %r<3>;
+.reg .b64 %rd<5>;
+
+
+.loc 2 75 1
+func_begin0:
+.loc 2 0 0
+
+.loc 2 75 1
+
+mov.u64 %SPL, __local_depot0;
+cvta.local.u64 %SP, %SPL;
+ld.param.u64 %rd1, [cudaMalloc_param_0];
+ld.param.u64 %rd2, [cudaMalloc_param_1];
+mov.u64 %rd3, %rd1;
+st.u64 [%SP+0], %rd3;
+mov.b64 %rd4, %rd2;
+func_exec_begin0:
+.loc 2 77 3
+tmp0:
+mov.u32 %r1, 999;
+mov.b32 %r2, %r1;
+st.param.b32 [func_retval0+0], %r2;
+ret;
+tmp1:
+func_end0:
+}
+
+
+.weak .func (.param .b32 func_retval0) cudaFuncGetAttributes(
+.param .b64 cudaFuncGetAttributes_param_0,
+.param .b64 cudaFuncGetAttributes_param_1
+)
+{
+.local .align 8 .b8 __local_depot1[8];
+.reg .b64 %SP;
+.reg .b64 %SPL;
+.reg .b32 %r<3>;
+.reg .b64 %rd<5>;
+
+
+.loc 2 80 1
+func_begin1:
+.loc 2 0 0
+
+.loc 2 80 1
+
+mov.u64 %SPL, __local_depot1;
+cvta.local.u64 %SP, %SPL;
+ld.param.u64 %rd1, [cudaFuncGetAttributes_param_0];
+ld.param.u64 %rd2, [cudaFuncGetAttributes_param_1];
+mov.u64 %rd3, %rd1;
+st.u64 [%SP+0], %rd3;
+mov.u64 %rd4, %rd2;
+func_exec_begin1:
+.loc 2 82 3
+tmp2:
+mov.u32 %r1, 999;
+mov.b32 %r2, %r1;
+st.param.b32 [func_retval0+0], %r2;
+ret;
+tmp3:
+func_end1:
+}
+
+
+.weak .func (.param .b32 func_retval0) cudaDeviceGetAttribute(
+.param .b64 cudaDeviceGetAttribute_param_0,
+.param .b32 cudaDeviceGetAttribute_param_1,
+.param .b32 cudaDeviceGetAttribute_param_2
+)
+{
+.reg .b32 %r<7>;
+.reg .b64 %rd<3>;
+
+
+.loc 2 85 1
+func_begin2:
+.loc 2 0 0
+
+.loc 2 85 1
+
+ld.param.u64 %rd1, [cudaDeviceGetAttribute_param_0];
+ld.param.u32 %r1, [cudaDeviceGetAttribute_param_1];
+ld.param.u32 %r2, [cudaDeviceGetAttribute_param_2];
+mov.u64 %rd2, %rd1;
+mov.b32 %r3, %r1;
+mov.b32 %r4, %r2;
+func_exec_begin2:
+.loc 2 87 3
+tmp4:
+mov.u32 %r5, 999;
+mov.b32 %r6, %r5;
+st.param.b32 [func_retval0+0], %r6;
+ret;
+tmp5:
+func_end2:
+}
+
+
+.weak .func (.param .b32 func_retval0) cudaGetDevice(
+.param .b64 cudaGetDevice_param_0
+)
+{
+.reg .b32 %r<3>;
+.reg .b64 %rd<3>;
+
+
+.loc 2 90 1
+func_begin3:
+.loc 2 0 0
+
+.loc 2 90 1
+
+ld.param.u64 %rd1, [cudaGetDevice_param_0];
+mov.u64 %rd2, %rd1;
+func_exec_begin3:
+.loc 2 92 3
+tmp6:
+mov.u32 %r1, 999;
+mov.b32 %r2, %r1;
+st.param.b32 [func_retval0+0], %r2;
+ret;
+tmp7:
+func_end3:
+}
+
+
+.weak .func (.param .b32 func_retval0) cudaOccupancyMaxActiveBlocksPerMultiprocessor(
+.param .b64 cudaOccupancyMaxActiveBlocksPerMultiprocessor_param_0,
+.param .b64 cudaOccupancyMaxActiveBlocksPerMultiprocessor_param_1,
+.param .b32 cudaOccupancyMaxActiveBlocksPerMultiprocessor_param_2,
+.param .b64 cudaOccupancyMaxActiveBlocksPerMultiprocessor_param_3
+)
+{
+.reg .b32 %r<5>;
+.reg .b64 %rd<7>;
+
+
+.loc 2 95 1
+func_begin4:
+.loc 2 0 0
+
+.loc 2 95 1
+
+ld.param.u64 %rd1, [cudaOccupancyMaxActiveBlocksPerMultiprocessor_param_0];
+ld.param.u64 %rd2, [cudaOccupancyMaxActiveBlocksPerMultiprocessor_param_1];
+ld.param.u32 %r1, [cudaOccupancyMaxActiveBlocksPerMultiprocessor_param_2];
+ld.param.u64 %rd3, [cudaOccupancyMaxActiveBlocksPerMultiprocessor_param_3];
+mov.u64 %rd4, %rd1;
+mov.u64 %rd5, %rd2;
+mov.b32 %r2, %r1;
+mov.b64 %rd6, %rd3;
+func_exec_begin4:
+.loc 2 97 3
+tmp8:
+mov.u32 %r3, 999;
+mov.b32 %r4, %r3;
+st.param.b32 [func_retval0+0], %r4;
+ret;
+tmp9:
+func_end4:
+}
+
+
+.weak .func (.param .b32 func_retval0) cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags(
+.param .b64 cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_0,
+.param .b64 cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_1,
+.param .b32 cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_2,
+.param .b64 cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_3,
+.param .b32 cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_4
+)
+{
+.reg .b32 %r<7>;
+.reg .b64 %rd<7>;
+
+
+.loc 2 100 1
+func_begin5:
+.loc 2 0 0
+
+.loc 2 100 1
+
+ld.param.u64 %rd1, [cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_0];
+ld.param.u64 %rd2, [cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_1];
+ld.param.u32 %r1, [cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_2];
+ld.param.u64 %rd3, [cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_3];
+ld.param.u32 %r2, [cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags_param_4];
+mov.u64 %rd4, %rd1;
+mov.u64 %rd5, %rd2;
+mov.b32 %r3, %r1;
+mov.b64 %rd6, %rd3;
+mov.b32 %r4, %r2;
+func_exec_begin5:
+.loc 2 102 3
+tmp10:
+mov.u32 %r5, 999;
+mov.b32 %r6, %r5;
+st.param.b32 [func_retval0+0], %r6;
+ret;
+tmp11:
+func_end5:
+}
+
+
+.visible .entry _Z9vectorAddPKfS0_Pfi(
+.param .u64 _Z9vectorAddPKfS0_Pfi_param_0,
+.param .u64 _Z9vectorAddPKfS0_Pfi_param_1,
+.param .u64 _Z9vectorAddPKfS0_Pfi_param_2,
+.param .u32 _Z9vectorAddPKfS0_Pfi_param_3
+)
+{
+.reg .pred %p<3>;
+.reg .f32 %f<4>;
+.reg .b32 %r<7>;
+.reg .b64 %rd<13>;
+
+
+.loc 1 33 1
+func_begin6:
+.loc 1 0 0
+
+.loc 1 33 1
+
+ld.param.u64 %rd1, [_Z9vectorAddPKfS0_Pfi_param_0];
+ld.param.u64 %rd2, [_Z9vectorAddPKfS0_Pfi_param_1];
+ld.param.u64 %rd3, [_Z9vectorAddPKfS0_Pfi_param_2];
+ld.param.u32 %r2, [_Z9vectorAddPKfS0_Pfi_param_3];
+func_exec_begin6:
+.loc 1 35 11
+tmp12:
+mov.u32 %r3, %ntid.x;
+mov.u32 %r4, %ctaid.x;
+mul.lo.s32 %r5, %r3, %r4;
+mov.u32 %r6, %tid.x;
+add.s32 %r1, %r5, %r6;
+tmp13:
+.loc 1 37 5
+setp.lt.s32 %p1, %r1, %r2;
+not.pred %p2, %p1;
+@%p2 bra BB6_2;
+bra.uni BB6_1;
+
+BB6_1:
+.loc 1 39 9
+tmp14:
+cvt.s64.s32 %rd4, %r1;
+shl.b64 %rd5, %rd4, 2;
+add.s64 %rd6, %rd1, %rd5;
+ld.f32 %f1, [%rd6];
+cvt.s64.s32 %rd7, %r1;
+shl.b64 %rd8, %rd7, 2;
+add.s64 %rd9, %rd2, %rd8;
+ld.f32 %f2, [%rd9];
+add.f32 %f3, %f1, %f2;
+cvt.s64.s32 %rd10, %r1;
+shl.b64 %rd11, %rd10, 2;
+add.s64 %rd12, %rd3, %rd11;
+st.f32 [%rd12], %f3;
+tmp15:
+
+BB6_2:
+.loc 1 41 1
+ret;
+tmp16:
+func_end6:
+}
+
+
+.visible .func _ZN4dim3C1Ejjj(
+.param .b64 _ZN4dim3C1Ejjj_param_0,
+.param .b32 _ZN4dim3C1Ejjj_param_1,
+.param .b32 _ZN4dim3C1Ejjj_param_2,
+.param .b32 _ZN4dim3C1Ejjj_param_3
+)
+{
+.reg .b32 %r<4>;
+.reg .b64 %rd<2>;
+
+
+.loc 3 421 1
+func_begin7:
+.loc 3 0 0
+
+.loc 3 421 1
+
+ld.param.u64 %rd1, [_ZN4dim3C1Ejjj_param_0];
+ld.param.u32 %r1, [_ZN4dim3C1Ejjj_param_1];
+ld.param.u32 %r2, [_ZN4dim3C1Ejjj_param_2];
+ld.param.u32 %r3, [_ZN4dim3C1Ejjj_param_3];
+func_exec_begin7:
+.loc 3 421 131
+tmp17:
+st.u32 [%rd1], %r1;
+.loc 3 421 138
+st.u32 [%rd1+4], %r2;
+.loc 3 421 145
+st.u32 [%rd1+8], %r3;
+.loc 3 421 152
+ret;
+tmp18:
+func_end7:
+}
+
+
+.visible .func _ZN4dim3C2Ejjj(
+.param .b64 _ZN4dim3C2Ejjj_param_0,
+.param .b32 _ZN4dim3C2Ejjj_param_1,
+.param .b32 _ZN4dim3C2Ejjj_param_2,
+.param .b32 _ZN4dim3C2Ejjj_param_3
+)
+{
+.reg .b32 %r<4>;
+.reg .b64 %rd<2>;
+
+
+.loc 3 421 1
+func_begin8:
+.loc 3 0 0
+
+.loc 3 421 1
+
+ld.param.u64 %rd1, [_ZN4dim3C2Ejjj_param_0];
+ld.param.u32 %r1, [_ZN4dim3C2Ejjj_param_1];
+ld.param.u32 %r2, [_ZN4dim3C2Ejjj_param_2];
+ld.param.u32 %r3, [_ZN4dim3C2Ejjj_param_3];
+func_exec_begin8:
+.loc 3 421 152
+tmp19:
+
+ {
+.reg .b32 temp_param_reg;
+
+ .param .b64 param0;
+st.param.b64 [param0+0], %rd1;
+.param .b32 param1;
+st.param.b32 [param1+0], %r1;
+.param .b32 param2;
+st.param.b32 [param2+0], %r2;
+.param .b32 param3;
+st.param.b32 [param3+0], %r3;
+call.uni
+_ZN4dim3C1Ejjj,
+(
+param0,
+param1,
+param2,
+param3
+);
+
+
+ }
+ ret;
+tmp20:
+func_end8:
+}
+
+
+.visible .func (.param .b32 func_retval0) _ZSt4fabsf(
+.param .b32 _ZSt4fabsf_param_0
+)
+{
+.reg .f32 %f<3>;
+
+
+.loc 4 241 1
+func_begin9:
+.loc 4 0 0
+
+.loc 4 241 1
+
+ld.param.f32 %f1, [_ZSt4fabsf_param_0];
+func_exec_begin9:
+.loc 4 242 12
+tmp21:
+
+ {
+.reg .b32 temp_param_reg;
+
+ .param .b32 param0;
+st.param.f32 [param0+0], %f1;
+.param .b32 retval0;
+call.uni (retval0),
+fabsf,
+(
+param0
+);
+ld.param.f32 %f2, [retval0+0];
+
+
+ }
+ st.param.f32 [func_retval0+0], %f2;
+ret;
+tmp22:
+func_end9:
+}
+
+.func (.param .b32 func_retval0) fabsf(
+.param .b32 fabsf_param_0
+)
+{
+.reg .f32 %f<3>;
+
+
+ld.param.f32 %f1, [fabsf_param_0];
+abs.f32 %f2, %f1;
+st.param.f32 [func_retval0+0], %f2;
+ret;
+}
+
+.file 1 "/home/vosen/cuda-samples-dbg/0_Simple/vectorAdd/vectorAdd.cu", 1595524614, 5649
+.file 2 "/usr/local/cuda-11.0/bin/../targets/x86_64-linux/include/cuda_device_runtime_api.h", 1595526477, 14970
+.file 3 "/usr/local/cuda-11.0/bin/../targets/x86_64-linux/include/vector_types.h", 1595526477, 13174
+.file 4 "/usr/include/c++/9/cmath", 1586428689, 49130
+.file 5 "/usr/local/cuda-11.0/bin/../targets/x86_64-linux/include/driver_types.h", 1595526477, 105017
+
+.section .debug_info {
+.b32 8837
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+}
+.section .debug_abbrev {
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+}
+.section .debug_ranges {
+}
+.section .debug_pubnames {
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+}
diff --git a/ptx/src/test/spirv_run/block.ptx b/ptx/src/test/spirv_run/block.ptx
new file mode 100644
index 0000000..03c552c
--- /dev/null
+++ b/ptx/src/test/spirv_run/block.ptx
@@ -0,0 +1,26 @@
+.version 6.5
+.target sm_30
+.address_size 64
+
+.visible .entry block(
+ .param .u64 input,
+ .param .u64 output
+)
+{
+ .reg .u64 in_addr;
+ .reg .u64 out_addr;
+ .reg .u64 temp;
+ .reg .u64 temp2;
+
+ ld.param.u64 in_addr, [input];
+ ld.param.u64 out_addr, [output];
+
+ ld.u64 temp, [in_addr];
+ add.u64 temp2, temp, 1;
+ {
+ .reg .u64 temp2;
+ add.u64 temp2, temp2, 1;
+ }
+ st.u64 [out_addr], temp2;
+ ret;
+}
diff --git a/ptx/src/test/spirv_run/block.spvtxt b/ptx/src/test/spirv_run/block.spvtxt
new file mode 100644
index 0000000..a780cc3
--- /dev/null
+++ b/ptx/src/test/spirv_run/block.spvtxt
@@ -0,0 +1,44 @@
+ OpCapability GenericPointer
+ OpCapability Linkage
+ OpCapability Addresses
+ OpCapability Kernel
+ OpCapability Int64
+ OpCapability Int8
+ %1 = OpExtInstImport "OpenCL.std"
+ OpMemoryModel Physical64 OpenCL
+ OpEntryPoint Kernel %5 "block"
+ %void = OpTypeVoid
+ %ulong = OpTypeInt 64 0
+ %4 = OpTypeFunction %void %ulong %ulong
+%_ptr_Function_ulong = OpTypePointer Function %ulong
+%_ptr_Generic_ulong = OpTypePointer Generic %ulong
+ %ulong_1 = OpConstant %ulong 1
+ %ulong_1_0 = OpConstant %ulong 1
+ %5 = OpFunction %void None %4
+ %6 = OpFunctionParameter %ulong
+ %7 = OpFunctionParameter %ulong
+ %25 = OpLabel
+ %8 = OpVariable %_ptr_Function_ulong Function
+ %9 = OpVariable %_ptr_Function_ulong Function
+ %10 = OpVariable %_ptr_Function_ulong Function
+ %11 = OpVariable %_ptr_Function_ulong Function
+ OpStore %8 %6
+ OpStore %9 %7
+ %14 = OpLoad %ulong %8
+ %23 = OpConvertUToPtr %_ptr_Generic_ulong %14
+ %13 = OpLoad %ulong %23
+ OpStore %10 %13
+ %16 = OpLoad %ulong %10
+ %15 = OpIAdd %ulong %16 %ulong_1
+ OpStore %11 %15
+ %12 = OpVariable %_ptr_Function_ulong Function
+ %18 = OpLoad %ulong %12
+ %17 = OpIAdd %ulong %18 %ulong_1_0
+ OpStore %12 %17
+ %19 = OpLoad %ulong %9
+ %20 = OpLoad %ulong %11
+ %24 = OpConvertUToPtr %_ptr_Generic_ulong %19
+ OpStore %24 %20
+ OpReturn
+ OpFunctionEnd
+ \ No newline at end of file
diff --git a/ptx/src/test/spirv_run/mod.rs b/ptx/src/test/spirv_run/mod.rs
index 257fad2..23852a1 100644
--- a/ptx/src/test/spirv_run/mod.rs
+++ b/ptx/src/test/spirv_run/mod.rs
@@ -50,6 +50,7 @@ test_ptx!(not, [0u64], [u64::max_value()]);
test_ptx!(shl, [11u64], [44u64]);
test_ptx!(cvt_sat_s_u, [-1i32], [0i32]);
test_ptx!(cvta, [3.0f32], [3.0f32]);
+test_ptx!(block, [1u64], [2u64]);
struct DisplayError<T: Debug> {
err: T,
diff --git a/ptx/src/translate.rs b/ptx/src/translate.rs
index b4d01eb..3fe01cf 100644
--- a/ptx/src/translate.rs
+++ b/ptx/src/translate.rs
@@ -271,7 +271,6 @@ fn normalize_predicates(
let mut result = Vec::with_capacity(func.len());
for s in func {
match s {
- ast::Statement::Block(_) => todo!(),
ast::Statement::Label(id) => result.push(Statement::Label(id)),
ast::Statement::Instruction(pred, inst) => {
if let Some(pred) = pred {
@@ -302,6 +301,8 @@ fn normalize_predicates(
ast::Statement::Variable(var) => {
result.push(Statement::Variable(var.name, var.v_type, var.space))
}
+ // Blocks are flattened when resolving ids
+ ast::Statement::Block(_) => unreachable!(),
}
}
result
@@ -659,7 +660,7 @@ fn emit_function_body_ops(
}
Statement::Instruction(inst) => match inst {
ast::Instruction::Abs(_, _) => todo!(),
- ast::Instruction::Call(_,_) => todo!(),
+ ast::Instruction::Call(_, _) => todo!(),
// SPIR-V does not support marking jumps as guaranteed-converged
ast::Instruction::Bra(_, arg) => {
builder.branch(arg.src)?;
@@ -1084,7 +1085,13 @@ fn expand_map_variables<'a>(
s: ast::Statement<ast::ParsedArgParams<'a>>,
) {
match s {
- ast::Statement::Block(_) => todo!(),
+ ast::Statement::Block(block) => {
+ id_defs.start_block();
+ for s in block {
+ expand_map_variables(id_defs, result, s);
+ }
+ id_defs.end_block();
+ }
ast::Statement::Label(name) => result.push(ast::Statement::Label(id_defs.get_id(name))),
ast::Statement::Instruction(p, i) => result.push(ast::Statement::Instruction(
p.map(|p| p.map_variable(&mut |id| id_defs.get_id(id))),
@@ -1118,7 +1125,7 @@ fn expand_map_variables<'a>(
struct StringIdResolver<'a> {
current_id: spirv::Word,
- variables: HashMap<Cow<'a, str>, spirv::Word>,
+ variables: Vec<HashMap<Cow<'a, str>, spirv::Word>>,
type_check: HashMap<u32, ast::Type>,
}
@@ -1126,7 +1133,7 @@ impl<'a> StringIdResolver<'a> {
fn new() -> Self {
StringIdResolver {
current_id: 0u32,
- variables: HashMap::new(),
+ variables: vec![HashMap::new(); 1],
type_check: HashMap::new(),
}
}
@@ -1138,13 +1145,30 @@ impl<'a> StringIdResolver<'a> {
}
}
+ fn start_block(&mut self) {
+ self.variables.push(HashMap::new())
+ }
+
+ fn end_block(&mut self) {
+ self.variables.pop();
+ }
+
fn get_id(&self, id: &'a str) -> spirv::Word {
- self.variables[id]
+ for scope in self.variables.iter().rev() {
+ match scope.get(id) {
+ Some(id) => return *id,
+ None => continue,
+ }
+ }
+ panic!()
}
fn add_def(&mut self, id: &'a str, typ: Option<ast::Type>) -> spirv::Word {
let numeric_id = self.current_id;
- self.variables.insert(Cow::Borrowed(id), numeric_id);
+ self.variables
+ .last_mut()
+ .unwrap()
+ .insert(Cow::Borrowed(id), numeric_id);
if let Some(typ) = typ {
self.type_check.insert(numeric_id, typ);
}
@@ -1162,6 +1186,8 @@ impl<'a> StringIdResolver<'a> {
let numeric_id = self.current_id;
for i in 0..count {
self.variables
+ .last_mut()
+ .unwrap()
.insert(Cow::Owned(format!("{}{}", base_id, i)), numeric_id + i);
self.type_check.insert(numeric_id + i, typ);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 13:31:58 +0000