| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-10-15 | Add or, mad, fma, min, max, selp, lg2, ex2, popc, rem | Andrzej Janik | |
| 2024-10-09 | Cleanup. Remove unused SPIR-V emit code and old compilation passes | Andrzej Janik | |
| 2024-10-06 | Support vector member read/write | Andrzej Janik | |
| 2024-10-06 | Implement call | Andrzej Janik | |
| 2024-09-30 | Add failing bfe test | Andrzej Janik | |
| 2024-09-26 | Add support for atom.cas | Andrzej Janik | |
| 2024-09-25 | Implement activemask | Andrzej Janik | |
| 2024-09-25 | Add ptx_impl bitcode module | Andrzej Janik | |
| 2024-09-23 | Refactor compilation passes (#270) | Andrzej Janik | |
| The overarching goal is to refactor all passes so they are module-scoped and not function-scoped. Additionally, make improvements to the most egregiously buggy/unfit passes (so the code is ready for the next major features: linking, ftz handling) and continue adding more code to the LLVM backend | |||
| 2024-09-13 | Connect new parser to LLVM bitcode backend (#269) | Andrzej Janik | |
| This is very incomplete. Just enough code to emit LLVM bitcode and continue further development | |||
| 2024-09-04 | PTX parser rewrite (#267) | Andrzej Janik | |
| Replaces traditional LALRPOP-based parser with winnow-based parser to handle out-of-order instruction modifer. Generate instruction type and instruction visitor from a macro instead of writing by hand. Add separate compilation path using the new parser that only works in tests for now | |||
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index : ZLUDA | |
| CUDA on AMD GPUs | vosen |
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