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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
target triple = "amdgcn-amd-amdhsa"
declare i32 @__zluda_ptx_impl__sreg_ntid(i8) #0
define protected amdgpu_kernel void @ntid(ptr addrspace(4) byref(i64) %"26", ptr addrspace(4) byref(i64) %"27") #1 {
"30":
%"9" = alloca i1, align 1, addrspace(5)
store i1 false, ptr addrspace(5) %"9", align 1
%"10" = alloca i1, align 1, addrspace(5)
store i1 false, ptr addrspace(5) %"10", align 1
%"4" = alloca i64, align 8, addrspace(5)
%"5" = alloca i64, align 8, addrspace(5)
%"6" = alloca i32, align 4, addrspace(5)
%"7" = alloca i32, align 4, addrspace(5)
%"16" = load i64, ptr addrspace(4) %"26", align 8
store i64 %"16", ptr addrspace(5) %"4", align 8
%"17" = load i64, ptr addrspace(4) %"27", align 8
store i64 %"17", ptr addrspace(5) %"5", align 8
%"19" = load i64, ptr addrspace(5) %"4", align 8
%"28" = inttoptr i64 %"19" to ptr
%"18" = load i32, ptr %"28", align 4
store i32 %"18", ptr addrspace(5) %"6", align 4
%"12" = call i32 @__zluda_ptx_impl__sreg_ntid(i8 0)
%0 = alloca i32, align 4, addrspace(5)
store i32 %"12", ptr addrspace(5) %0, align 4
%"20" = load i32, ptr addrspace(5) %0, align 4
store i32 %"20", ptr addrspace(5) %"7", align 4
%"22" = load i32, ptr addrspace(5) %"6", align 4
%"23" = load i32, ptr addrspace(5) %"7", align 4
%"21" = add i32 %"22", %"23"
store i32 %"21", ptr addrspace(5) %"6", align 4
%"24" = load i64, ptr addrspace(5) %"5", align 8
%"25" = load i32, ptr addrspace(5) %"6", align 4
%"29" = inttoptr i64 %"24" to ptr
store i32 %"25", ptr %"29", align 4
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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