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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
target triple = "amdgcn-amd-amdhsa"
declare i32 @__zluda_ptx_impl__vote_sync_ballot_b32_32(i1, i32) #0
define protected amdgpu_kernel void @vote_ballot(ptr addrspace(4) byref(i64) %"41", ptr addrspace(4) byref(i64) %"42") #1 {
"51":
%"10" = alloca i1, align 1, addrspace(5)
store i1 false, ptr addrspace(5) %"10", align 1
%"11" = alloca i1, align 1, addrspace(5)
store i1 false, ptr addrspace(5) %"11", align 1
%"4" = alloca i64, align 8, addrspace(5)
%"5" = alloca i64, align 8, addrspace(5)
%"6" = alloca i32, align 4, addrspace(5)
%"7" = alloca i32, align 4, addrspace(5)
%"8" = alloca i32, align 4, addrspace(5)
%"9" = alloca i32, align 4, addrspace(5)
%"12" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"12", ptr addrspace(5) %"5", align 8
%"43" = call i32 @__zluda_ptx_impl__vote_sync_ballot_b32_32(i1 true, i32 1)
store i32 %"43", ptr addrspace(5) %"6", align 4
%"44" = call i32 @__zluda_ptx_impl__vote_sync_ballot_b32_32(i1 false, i32 16777215)
store i32 %"44", ptr addrspace(5) %"7", align 4
%"45" = call i32 @__zluda_ptx_impl__vote_sync_ballot_b32_32(i1 true, i32 2)
store i32 %"45", ptr addrspace(5) %"8", align 4
%"46" = call i32 @__zluda_ptx_impl__vote_sync_ballot_b32_32(i1 true, i32 3)
store i32 %"46", ptr addrspace(5) %"9", align 4
%"17" = load i64, ptr addrspace(5) %"5", align 8
%"18" = load i32, ptr addrspace(5) %"6", align 4
%"47" = inttoptr i64 %"17" to ptr
%"57" = getelementptr inbounds i8, ptr %"47", i64 0
store i32 %"18", ptr %"57", align 4
%"19" = load i64, ptr addrspace(5) %"5", align 8
%"20" = load i32, ptr addrspace(5) %"7", align 4
%"48" = inttoptr i64 %"19" to ptr
%"59" = getelementptr inbounds i8, ptr %"48", i64 4
store i32 %"20", ptr %"59", align 4
%"21" = load i64, ptr addrspace(5) %"5", align 8
%"22" = load i32, ptr addrspace(5) %"8", align 4
%"49" = inttoptr i64 %"21" to ptr
%"61" = getelementptr inbounds i8, ptr %"49", i64 8
store i32 %"22", ptr %"61", align 4
%"23" = load i64, ptr addrspace(5) %"5", align 8
%"24" = load i32, ptr addrspace(5) %"9", align 4
%"50" = inttoptr i64 %"23" to ptr
%"63" = getelementptr inbounds i8, ptr %"50", i64 12
store i32 %"24", ptr %"63", align 4
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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