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| author | MITSUNARI Shigeo <[email protected]> | 2024-10-13 15:27:05 +0900 |
|---|---|---|
| committer | MITSUNARI Shigeo <[email protected]> | 2024-10-13 15:27:05 +0900 |
| commit | f6c66cf6b81f7a063a930cdfc0a62c68e6e2d0fc (patch) | |
| tree | 1f0890d9bf310f34d5f0ef7132d13ea613187480 /gen | |
| parent | f3f2dd2d748859fd4438ab596950ba52769607a4 (diff) | |
| download | xbyak-f6c66cf6b81f7a063a930cdfc0a62c68e6e2d0fc.tar.gz xbyak-f6c66cf6b81f7a063a930cdfc0a62c68e6e2d0fc.zip | |
vpdpb[su,uu,ss]d[,s] support avx10.2
Diffstat (limited to 'gen')
| -rw-r--r-- | gen/gen_avx512.cpp | 8 | ||||
| -rw-r--r-- | gen/gen_code.cpp | 10 |
2 files changed, 10 insertions, 8 deletions
diff --git a/gen/gen_avx512.cpp b/gen/gen_avx512.cpp index 9159a64..ed7440c 100644 --- a/gen/gen_avx512.cpp +++ b/gen/gen_avx512.cpp @@ -468,10 +468,12 @@ void putX_X_XM_IMM_AVX10() bool hasIMM; } tbl[] = { { 0x50, "vpdpbssd", T_F2|T_0F38|T_YMM, T_W0, T_EW0|T_B32, 1, false }, + { 0x51, "vpdpbssds", T_F2|T_0F38|T_YMM, T_W0, T_EW0|T_B32, 1, false }, + { 0x50, "vpdpbsud", T_F3|T_0F38|T_YMM, T_W0, T_EW0|T_B32, 1, false }, + { 0x51, "vpdpbsuds", T_F3|T_0F38|T_YMM, T_W0, T_EW0|T_B32, 1, false }, + { 0x50, "vpdpbuud", T_0F38|T_YMM, T_W0, T_EW0|T_B32, 1, false }, + { 0x51, "vpdpbuuds", T_0F38|T_YMM, T_W0, T_EW0|T_B32, 1, false }, #if 0 - { 0x51, "vpdpbssds", T_MUST_EVEX | T_YMM | T_F2 | T_0F38 | T_EW0 | T_B32, false }, - { 0x50, "vpdpbsud", T_MUST_EVEX | T_YMM | T_F3 | T_0F38 | T_EW0 | T_B32, false }, - { 0x51, "vpdpbsuds", T_MUST_EVEX | T_YMM | T_F3 | T_0F38 | T_EW0 | T_B32, false }, { 0x50, "vpdpbuud", T_MUST_EVEX | T_YMM | T_0F38 | T_EW0 | T_B32, false }, { 0x51, "vpdpbuuds", T_MUST_EVEX | T_YMM | T_0F38 | T_EW0 | T_B32, false }, #endif diff --git a/gen/gen_code.cpp b/gen/gen_code.cpp index caa9e79..a71d416 100644 --- a/gen/gen_code.cpp +++ b/gen/gen_code.cpp @@ -1908,11 +1908,11 @@ void put() uint64_t type; } tbl[] = { // { 0x50, "vpdpbssd", T_F2 | T_0F38 | T_W0 | T_YMM }, - { 0x51, "vpdpbssds", T_F2 | T_0F38 | T_W0 | T_YMM }, - { 0x50, "vpdpbsud", T_F3 | T_0F38 | T_W0 | T_YMM }, - { 0x51, "vpdpbsuds", T_F3 | T_0F38 | T_W0 | T_YMM }, - { 0x50, "vpdpbuud", T_0F38 | T_W0 | T_YMM }, - { 0x51, "vpdpbuuds", T_0F38 | T_W0 | T_YMM }, +// { 0x51, "vpdpbssds", T_F2 | T_0F38 | T_W0 | T_YMM }, +// { 0x50, "vpdpbsud", T_F3 | T_0F38 | T_W0 | T_YMM }, +// { 0x51, "vpdpbsuds", T_F3 | T_0F38 | T_W0 | T_YMM }, +// { 0x50, "vpdpbuud", T_0F38 | T_W0 | T_YMM }, +// { 0x51, "vpdpbuuds", T_0F38 | T_W0 | T_YMM }, { 0xD2, "vpdpwsud", T_F3 | T_0F38 | T_W0 | T_YMM }, { 0xD3, "vpdpwsuds", T_F3 | T_0F38 | T_W0 | T_YMM }, |