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-rw-r--r--gen/gen_code.cpp20
-rw-r--r--xbyak/xbyak.h26
-rw-r--r--xbyak/xbyak_mnemonic.h88
3 files changed, 67 insertions, 67 deletions
diff --git a/gen/gen_code.cpp b/gen/gen_code.cpp
index 82aacf1..7f394a3 100644
--- a/gen/gen_code.cpp
+++ b/gen/gen_code.cpp
@@ -622,7 +622,7 @@ void put()
const char *msg = "//-V524"; // disable warning of PVS-Studio
for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) {
const Tbl *p = &tbl[i];
- printf("void cmov%s(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | %d); }%s\n", p->name, p->ext, msg);
+ printf("void cmov%s(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | %d, op.isREG(16|i32e)); }%s\n", p->name, p->ext, msg);
printf("void j%s(std::string label, LabelType type = T_AUTO) { opJmp(label, type, 0x%02X, 0x%02X, 0x%02X); }%s\n", p->name, p->ext | 0x70, p->ext | 0x80, 0x0F, msg);
printf("void j%s(const Label& label, LabelType type = T_AUTO) { opJmp(label, type, 0x%02X, 0x%02X, 0x%02X); }%s\n", p->name, p->ext | 0x70, p->ext | 0x80, 0x0F, msg);
printf("void j%s(const char *label, LabelType type = T_AUTO) { j%s(std::string(label), type); }%s\n", p->name, p->name, msg);
@@ -856,7 +856,7 @@ void put()
};
for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) {
const Tbl *p = &tbl[i];
- printf("void %s(const Operand& op, const Reg& reg) { opRO(reg, op, op.isREG(16|i32e) && op.getBit() == reg.getBit(), T_0F, 0x%02X); }\n", p->name, p->code);
+ printf("void %s(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0x%02X, op.isREG(16|i32e) && op.getBit() == reg.getBit()); }\n", p->name, p->code);
printf("void %s(const Operand& op, uint8_t imm) { opRext(op, 16|i32e, %d, T_0F, 0xba, false, 1); db(imm); }\n", p->name, p->ext);
}
}
@@ -924,7 +924,7 @@ void put()
};
for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) {
const Tbl *p = &tbl[i];
- printf("void %s(const Reg&reg, const Operand& op) { opRO(reg, op, op.isREG(16|i32e), T_0F, 0x%02X); }\n", p->name, p->code);
+ printf("void %s(const Reg&reg, const Operand& op) { opRO(reg, op, T_0F, 0x%02X, op.isREG(16|i32e)); }\n", p->name, p->code);
}
}
{
@@ -1056,7 +1056,7 @@ void put()
};
for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) {
const Tbl *p = &tbl[i];
- printf("void %s(const Reg32e& reg, const Operand& op) { if (opROO(Reg(), op, reg, T_%02X, 0x66)) return; opSSE(reg, op, T_%02X | T_0F38, 0xF6, isREG32_REG32orMEM); }\n", p->name, p->prefix, p->prefix);
+ printf("void %s(const Reg32e& reg, const Operand& op) { if (!reg.isREG(16|i32e) && reg.getBit() == op.getBit()) XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER) if (opROO(Reg(), op, reg, T_%02X, 0x66)) return; opRO(reg, op, T_%02X | T_0F38, 0xF6); }\n", p->name, p->prefix, p->prefix);
printf("void %s(const Reg32e& d, const Reg32e& reg, const Operand& op) { opROO(d, op, reg, T_%02X, 0x66); }\n", p->name, p->prefix);
}
}
@@ -1073,7 +1073,7 @@ void put()
puts("void bndcn(const BoundsReg& bnd, const Operand& op) { opRext(op, i32e, bnd.getIdx(), T_F2 | T_0F, 0x1B, !op.isMEM()); }");
puts("void bndldx(const BoundsReg& bnd, const Address& addr) { opMIB(addr, bnd, T_0F, 0x1A); }");
puts("void bndmk(const BoundsReg& bnd, const Address& addr) { opMR(addr, bnd, T_F3 | T_0F, 0x1B); }");
- puts("void bndmov(const BoundsReg& bnd, const Operand& op) { opRO(bnd, op, op.isBNDREG(), T_66 | T_0F, 0x1A); }");
+ puts("void bndmov(const BoundsReg& bnd, const Operand& op) { opRO(bnd, op, T_66 | T_0F, 0x1A, op.isBNDREG()); }");
puts("void bndmov(const Address& addr, const BoundsReg& bnd) { opMR(addr, bnd, T_66 | T_0F, 0x1B); }");
puts("void bndstx(const Address& addr, const BoundsReg& bnd) { opMIB(addr, bnd, T_0F, 0x1B); }");
}
@@ -1084,8 +1084,8 @@ void put()
puts("void ret(int imm = 0) { if (imm) { db(0xC2); dw(imm); } else { db(0xC3); } }");
puts("void retf(int imm = 0) { if (imm) { db(0xCA); dw(imm); } else { db(0xCB); } }");
- puts("void xadd(const Operand& op, const Reg& reg) { opRO(reg, op, op.getBit() == reg.getBit(), T_0F, 0xC0 | (reg.isBit(8) ? 0 : 1)); }");
- puts("void cmpxchg(const Operand& op, const Reg& reg) { opRO(reg, op, op.getBit() == reg.getBit(), T_0F, 0xB0 | (reg.isBit(8) ? 0 : 1)); }");
+ puts("void xadd(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0xC0 | (reg.isBit(8) ? 0 : 1), op.getBit() == reg.getBit()); }");
+ puts("void cmpxchg(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0xB0 | (reg.isBit(8) ? 0 : 1), op.getBit() == reg.getBit()); }");
puts("void movbe(const Reg& reg, const Address& addr) { opMR(addr, reg, T_0F38, 0xF0); }");
puts("void movbe(const Address& addr, const Reg& reg) { opMR(addr, reg, T_0F38, 0xF1); }");
puts("void movdiri(const Address& addr, const Reg32e& reg) { opMR(addr, reg, T_0F38, 0xF9); }");
@@ -1117,11 +1117,11 @@ void put()
puts("void movd(const Mmx& mmx, const Reg32& reg) { if (mmx.isXMM()) db(0x66); opRR(mmx, reg, T_0F, 0x6E); }");
puts("void movq2dq(const Xmm& xmm, const Mmx& mmx) { opRR(xmm, mmx, T_F3 | T_0F, 0xD6); }");
puts("void movdq2q(const Mmx& mmx, const Xmm& xmm) { opRR(mmx, xmm, T_F2 | T_0F, 0xD6); }");
- puts("void movq(const Mmx& mmx, const Operand& op) { if (mmx.isXMM()) db(0xF3); opRO(mmx, op, mmx.getKind() == op.getKind(), T_0F, mmx.isXMM() ? 0x7E : 0x6F); }");
+ puts("void movq(const Mmx& mmx, const Operand& op) { if (mmx.isXMM()) db(0xF3); opRO(mmx, op, T_0F, mmx.isXMM() ? 0x7E : 0x6F, mmx.getKind() == op.getKind()); }");
puts("void movq(const Address& addr, const Mmx& mmx) { if (mmx.isXMM()) db(0x66); opMR(addr, mmx, T_0F, mmx.isXMM() ? 0xD6 : 0x7F); }");
puts("void rdrand(const Reg& r) { if (r.isBit(8)) XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER) opRR(Reg(6, Operand::REG, r.getBit()), r, T_0F, 0xC7); }");
puts("void rdseed(const Reg& r) { if (r.isBit(8)) XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER) opRR(Reg(7, Operand::REG, r.getBit()), r, T_0F, 0xC7); }");
- puts("void crc32(const Reg32e& reg, const Operand& op) { if (reg.isBit(32) && op.isBit(16)) db(0x66); opRO(reg, op, true, T_F2 | T_0F38, 0xF0 | (op.isBit(8) ? 0 : 1)); }");
+ puts("void crc32(const Reg32e& reg, const Operand& op) { if (reg.isBit(32) && op.isBit(16)) db(0x66); opRO(reg, op, T_F2 | T_0F38, 0xF0 | (op.isBit(8) ? 0 : 1)); }");
puts("void tpause(const Reg32& r) { int idx = r.getIdx(); if (idx > 7) XBYAK_THROW(ERR_BAD_PARAMETER) db(0x66); db(0x0F); db(0xAE); setModRM(3, 6, idx); }");
puts("void umonitor(const Reg& r) { int idx = r.getIdx(); if (idx > 7) XBYAK_THROW(ERR_BAD_PARAMETER) int bit = r.getBit(); if (BIT != bit) { if ((BIT == 32 && bit == 16) || (BIT == 64 && bit == 32)) { db(0x67); } else { XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER) } } db(0xF3); db(0x0F); db(0xAE); setModRM(3, 6, idx); }");
puts("void umwait(const Reg32& r) { int idx = r.getIdx(); if (idx > 7) XBYAK_THROW(ERR_BAD_PARAMETER) db(0xF2); db(0x0F); db(0xAE); setModRM(3, 6, idx); }");
@@ -1902,7 +1902,7 @@ void put64()
putMemOp("fxrstor64", "T_0F", 1, 0xAE, 64);
puts("void movq(const Reg64& reg, const Mmx& mmx) { if (mmx.isXMM()) db(0x66); opRR(mmx, reg, T_0F, 0x7E); }");
puts("void movq(const Mmx& mmx, const Reg64& reg) { if (mmx.isXMM()) db(0x66); opRR(mmx, reg, T_0F, 0x6E); }");
- puts("void movsxd(const Reg64& reg, const Operand& op) { if (!op.isBit(32)) XBYAK_THROW(ERR_BAD_COMBINATION) opRO(reg, op, true, 0, 0x63); }");
+ puts("void movsxd(const Reg64& reg, const Operand& op) { if (!op.isBit(32)) XBYAK_THROW(ERR_BAD_COMBINATION) opRO(reg, op, 0, 0x63); }");
puts("void pextrq(const Operand& op, const Xmm& xmm, uint8_t imm) { if (!op.isREG(64) && !op.isMEM()) XBYAK_THROW(ERR_BAD_COMBINATION) opSSE(Reg64(xmm.getIdx()), op, T_66 | T_0F3A, 0x16, 0, imm); }");
puts("void pinsrq(const Xmm& xmm, const Operand& op, uint8_t imm) { if (!op.isREG(64) && !op.isMEM()) XBYAK_THROW(ERR_BAD_COMBINATION) opSSE(Reg64(xmm.getIdx()), op, T_66 | T_0F3A, 0x22, 0, imm); }");
puts("void senduipi(const Reg64& r) { opRR(Reg32(6), r.cvt32(), T_F3 | T_0F, 0xC7); }");
diff --git a/xbyak/xbyak.h b/xbyak/xbyak.h
index e1ad130..8388a5b 100644
--- a/xbyak/xbyak.h
+++ b/xbyak/xbyak.h
@@ -2110,7 +2110,7 @@ private:
{
if (isValid && !isValid(r, op)) XBYAK_THROW(ERR_BAD_COMBINATION)
if (!isValidSSE(r) || !isValidSSE(op)) XBYAK_THROW(ERR_NOT_SUPPORTED)
- opRO(r, op, true, type, code, (imm8 != NONE) ? 1 : 0);
+ opRO(r, op, type, code, true, (imm8 != NONE) ? 1 : 0);
if (imm8 != NONE) db(imm8);
}
void opMMX_IMM(const Mmx& mmx, int imm8, int code, int ext)
@@ -2173,7 +2173,7 @@ private:
opRext(op, 0, ext, 0, 0xD2);
}
// condR assumes that op.isREG() is true
- void opRO(const Reg& r, const Operand& op, bool condR, int type, int code, int immSize = 0)
+ void opRO(const Reg& r, const Operand& op, int type, int code, bool condR = true, int immSize = 0)
{
if (op.isMEM()) {
opMR(op.getAddress(), r, type, code, immSize);
@@ -2186,8 +2186,8 @@ private:
void opShxd(const Operand& op, const Reg& reg, uint8_t imm, int code, const Reg8 *_cl = 0)
{
if (_cl && _cl->getIdx() != Operand::CL) XBYAK_THROW(ERR_BAD_COMBINATION)
- if (!reg.isREG(16 | i32e)) XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER)
- opRO(reg, op, true, T_0F, code | (_cl ? 1 : 0), _cl ? 0 : 1);
+ if (!reg.isREG(16|i32e)) XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER)
+ opRO(reg, op, T_0F, code | (_cl ? 1 : 0), true, _cl ? 0 : 1);
if (!_cl) db(imm);
}
// (REG, REG|MEM), (MEM, REG)
@@ -2197,7 +2197,7 @@ private:
if (!op1.isREG()) XBYAK_THROW(ERR_BAD_COMBINATION)
opMR(op2.getAddress(), op1.getReg(), 0, code | 2);
} else {
- opRO(static_cast<const Reg&>(op2), op1, op1.getKind() == op2.getKind(), 0, code);
+ opRO(static_cast<const Reg&>(op2), op1, 0, code, op1.getKind() == op2.getKind());
}
}
uint32_t getImmBit(const Operand& op, uint32_t imm)
@@ -2315,7 +2315,7 @@ private:
if (op.isBit(32)) XBYAK_THROW(ERR_BAD_COMBINATION)
int w = op.isBit(16);
if (!(reg.isREG() && (reg.getBit() > op.getBit()))) XBYAK_THROW(ERR_BAD_COMBINATION)
- opRO(reg, op, true, T_0F, code | w);
+ opRO(reg, op, T_0F, code | w);
}
void opFpuMem(const Address& addr, uint8_t m16, uint8_t m32, uint8_t m64, uint8_t ext, uint8_t m64ext)
{
@@ -2459,7 +2459,7 @@ private:
bool is16bit = reg.isREG(16) && (op.isREG(16) || op.isMEM());
if (!is16bit && !(reg.isREG(i32e) && (op.isREG(reg.getBit()) || op.isMEM()))) XBYAK_THROW(ERR_BAD_COMBINATION)
if (is16bit) db(0x66);
- opRO(reg.changeBit(i32e == 32 ? 32 : reg.getBit()), op, true, T_F3 | T_0F, code);
+ opRO(reg.changeBit(i32e == 32 ? 32 : reg.getBit()), op, T_F3 | T_0F, code);
}
void opGather(const Xmm& x1, const Address& addr, const Xmm& x2, int type, uint8_t code, int mode)
{
@@ -2682,7 +2682,7 @@ public:
void test(const Operand& op, const Reg& reg)
{
- opRO(reg, op, op.getKind() == reg.getKind(), 0, 0x84);
+ opRO(reg, op, 0, 0x84, op.getKind() == reg.getKind());
}
void test(const Operand& op, uint32_t imm)
{
@@ -2698,13 +2698,13 @@ public:
}
void imul(const Reg& reg, const Operand& op)
{
- opRO(reg, op, reg.getKind() == op.getKind(), T_0F, 0xAF);
+ opRO(reg, op, T_0F, 0xAF, reg.getKind() == op.getKind());
}
void imul(const Reg& reg, const Operand& op, int imm)
{
int s = inner::IsInDisp8(imm) ? 1 : 0;
int immSize = s ? 1 : reg.isREG(16) ? 2 : 4;
- opRO(reg, op, reg.getKind() == op.getKind(), 0, 0x69 | (s << 1), immSize);
+ opRO(reg, op, 0, 0x69 | (s << 1), reg.getKind() == op.getKind(), immSize);
db(imm, immSize);
}
void push(const Operand& op) { opPushPop(op, 0xFF, 6, 0x50); }
@@ -2811,7 +2811,7 @@ public:
rex(*p2, *p1); db(0x90 | (p2->getIdx() & 7));
return;
}
- opRO(static_cast<const Reg&>(*p1), *p2, (p1->isREG() && (p1->getBit() == p2->getBit())), 0, 0x86 | (p1->isBit(8) ? 0 : 1));
+ opRO(static_cast<const Reg&>(*p1), *p2, 0, 0x86 | (p1->isBit(8) ? 0 : 1), (p1->isREG() && (p1->getBit() == p2->getBit())));
}
#ifndef XBYAK_DISABLE_SEGMENT
@@ -2856,11 +2856,11 @@ public:
}
void mov(const Operand& op, const Segment& seg)
{
- opRO(Reg8(seg.getIdx()), op, op.isREG(16|i32e), 0, 0x8C);
+ opRO(Reg8(seg.getIdx()), op, 0, 0x8C, op.isREG(16|i32e));
}
void mov(const Segment& seg, const Operand& op)
{
- opRO(Reg8(seg.getIdx()), op.isREG(16|i32e) ? static_cast<const Operand&>(op.getReg().cvt32()) : op, op.isREG(16|i32e), 0, 0x8E);
+ opRO(Reg8(seg.getIdx()), op.isREG(16|i32e) ? static_cast<const Operand&>(op.getReg().cvt32()) : op, 0, 0x8E, op.isREG(16|i32e));
}
// (r, r, m) or (r, m, r)
diff --git a/xbyak/xbyak_mnemonic.h b/xbyak/xbyak_mnemonic.h
index 3473149..9aed4bb 100644
--- a/xbyak/xbyak_mnemonic.h
+++ b/xbyak/xbyak_mnemonic.h
@@ -6,7 +6,7 @@ void adc(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x10); }
void adc(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, 0, 2); }
void adc(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, 0, 0x10); }
void adcx(const Reg32e& d, const Reg32e& reg, const Operand& op) { opROO(d, op, reg, T_66, 0x66); }
-void adcx(const Reg32e& reg, const Operand& op) { if (opROO(Reg(), op, reg, T_66, 0x66)) return; opSSE(reg, op, T_66 | T_0F38, 0xF6, isREG32_REG32orMEM); }
+void adcx(const Reg32e& reg, const Operand& op) { if (!reg.isREG(16|i32e) && reg.getBit() == op.getBit()) XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER) if (opROO(Reg(), op, reg, T_66, 0x66)) return; opRO(reg, op, T_66 | T_0F38, 0xF6); }
void add(const Operand& op, uint32_t imm) { opOI(op, imm, 0x00, 0); }
void add(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x00); }
void add(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, 0, 0); }
@@ -18,7 +18,7 @@ void addss(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_F3, 0x58
void addsubpd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_66 | T_0F | T_YMM, 0xD0, isXMM_XMMorMEM); }
void addsubps(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_F2 | T_0F | T_YMM, 0xD0, isXMM_XMMorMEM); }
void adox(const Reg32e& d, const Reg32e& reg, const Operand& op) { opROO(d, op, reg, T_F3, 0x66); }
-void adox(const Reg32e& reg, const Operand& op) { if (opROO(Reg(), op, reg, T_F3, 0x66)) return; opSSE(reg, op, T_F3 | T_0F38, 0xF6, isREG32_REG32orMEM); }
+void adox(const Reg32e& reg, const Operand& op) { if (!reg.isREG(16|i32e) && reg.getBit() == op.getBit()) XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER) if (opROO(Reg(), op, reg, T_F3, 0x66)) return; opRO(reg, op, T_F3 | T_0F38, 0xF6); }
void aesdec(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_66 | T_0F38 | T_YMM | T_EVEX, 0xDE, isXMM_XMMorMEM); }
void aesdeclast(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_66 | T_0F38 | T_YMM | T_EVEX, 0xDF, isXMM_XMMorMEM); }
void aesenc(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_66 | T_0F38 | T_YMM | T_EVEX, 0xDC, isXMM_XMMorMEM); }
@@ -51,18 +51,18 @@ void bndcu(const BoundsReg& bnd, const Operand& op) { opRext(op, i32e, bnd.getId
void bndldx(const BoundsReg& bnd, const Address& addr) { opMIB(addr, bnd, T_0F, 0x1A); }
void bndmk(const BoundsReg& bnd, const Address& addr) { opMR(addr, bnd, T_F3 | T_0F, 0x1B); }
void bndmov(const Address& addr, const BoundsReg& bnd) { opMR(addr, bnd, T_66 | T_0F, 0x1B); }
-void bndmov(const BoundsReg& bnd, const Operand& op) { opRO(bnd, op, op.isBNDREG(), T_66 | T_0F, 0x1A); }
+void bndmov(const BoundsReg& bnd, const Operand& op) { opRO(bnd, op, T_66 | T_0F, 0x1A, op.isBNDREG()); }
void bndstx(const Address& addr, const BoundsReg& bnd) { opMIB(addr, bnd, T_0F, 0x1B); }
-void bsf(const Reg&reg, const Operand& op) { opRO(reg, op, op.isREG(16|i32e), T_0F, 0xBC); }
-void bsr(const Reg&reg, const Operand& op) { opRO(reg, op, op.isREG(16|i32e), T_0F, 0xBD); }
+void bsf(const Reg&reg, const Operand& op) { opRO(reg, op, T_0F, 0xBC, op.isREG(16|i32e)); }
+void bsr(const Reg&reg, const Operand& op) { opRO(reg, op, T_0F, 0xBD, op.isREG(16|i32e)); }
void bswap(const Reg32e& reg) { opRR(Reg32(1), reg, 0, 0x0F); }
-void bt(const Operand& op, const Reg& reg) { opRO(reg, op, op.isREG(16|i32e) && op.getBit() == reg.getBit(), T_0F, 0xA3); }
+void bt(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0xA3, op.isREG(16|i32e) && op.getBit() == reg.getBit()); }
void bt(const Operand& op, uint8_t imm) { opRext(op, 16|i32e, 4, T_0F, 0xba, false, 1); db(imm); }
-void btc(const Operand& op, const Reg& reg) { opRO(reg, op, op.isREG(16|i32e) && op.getBit() == reg.getBit(), T_0F, 0xBB); }
+void btc(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0xBB, op.isREG(16|i32e) && op.getBit() == reg.getBit()); }
void btc(const Operand& op, uint8_t imm) { opRext(op, 16|i32e, 7, T_0F, 0xba, false, 1); db(imm); }
-void btr(const Operand& op, const Reg& reg) { opRO(reg, op, op.isREG(16|i32e) && op.getBit() == reg.getBit(), T_0F, 0xB3); }
+void btr(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0xB3, op.isREG(16|i32e) && op.getBit() == reg.getBit()); }
void btr(const Operand& op, uint8_t imm) { opRext(op, 16|i32e, 6, T_0F, 0xba, false, 1); db(imm); }
-void bts(const Operand& op, const Reg& reg) { opRO(reg, op, op.isREG(16|i32e) && op.getBit() == reg.getBit(), T_0F, 0xAB); }
+void bts(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0xAB, op.isREG(16|i32e) && op.getBit() == reg.getBit()); }
void bts(const Operand& op, uint8_t imm) { opRext(op, 16|i32e, 5, T_0F, 0xba, false, 1); db(imm); }
void bzhi(const Reg32e& r1, const Operand& op, const Reg32e& r2) { opRRO(r1, r2, op, T_0F38, 0xf5); }
void cbw() { db(0x66); db(0x98); }
@@ -76,36 +76,36 @@ void cli() { db(0xFA); }
void clwb(const Address& addr) { opMR(addr, esi, T_66 | T_0F, 0xAE); }
void clzero() { db(0x0F); db(0x01); db(0xFC); }
void cmc() { db(0xF5); }
-void cmova(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 7); }//-V524
-void cmovae(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 3); }//-V524
-void cmovb(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 2); }//-V524
-void cmovbe(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 6); }//-V524
-void cmovc(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 2); }//-V524
-void cmove(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 4); }//-V524
-void cmovg(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 15); }//-V524
-void cmovge(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 13); }//-V524
-void cmovl(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 12); }//-V524
-void cmovle(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 14); }//-V524
-void cmovna(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 6); }//-V524
-void cmovnae(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 2); }//-V524
-void cmovnb(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 3); }//-V524
-void cmovnbe(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 7); }//-V524
-void cmovnc(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 3); }//-V524
-void cmovne(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 5); }//-V524
-void cmovng(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 14); }//-V524
-void cmovnge(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 12); }//-V524
-void cmovnl(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 13); }//-V524
-void cmovnle(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 15); }//-V524
-void cmovno(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 1); }//-V524
-void cmovnp(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 11); }//-V524
-void cmovns(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 9); }//-V524
-void cmovnz(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 5); }//-V524
-void cmovo(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 0); }//-V524
-void cmovp(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 10); }//-V524
-void cmovpe(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 10); }//-V524
-void cmovpo(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 11); }//-V524
-void cmovs(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 8); }//-V524
-void cmovz(const Reg& reg, const Operand& op) { opRO(reg, op, op.isREG(16 | i32e), T_0F, 0x40 | 4); }//-V524
+void cmova(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 7, op.isREG(16|i32e)); }//-V524
+void cmovae(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 3, op.isREG(16|i32e)); }//-V524
+void cmovb(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 2, op.isREG(16|i32e)); }//-V524
+void cmovbe(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 6, op.isREG(16|i32e)); }//-V524
+void cmovc(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 2, op.isREG(16|i32e)); }//-V524
+void cmove(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 4, op.isREG(16|i32e)); }//-V524
+void cmovg(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 15, op.isREG(16|i32e)); }//-V524
+void cmovge(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 13, op.isREG(16|i32e)); }//-V524
+void cmovl(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 12, op.isREG(16|i32e)); }//-V524
+void cmovle(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 14, op.isREG(16|i32e)); }//-V524
+void cmovna(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 6, op.isREG(16|i32e)); }//-V524
+void cmovnae(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 2, op.isREG(16|i32e)); }//-V524
+void cmovnb(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 3, op.isREG(16|i32e)); }//-V524
+void cmovnbe(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 7, op.isREG(16|i32e)); }//-V524
+void cmovnc(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 3, op.isREG(16|i32e)); }//-V524
+void cmovne(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 5, op.isREG(16|i32e)); }//-V524
+void cmovng(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 14, op.isREG(16|i32e)); }//-V524
+void cmovnge(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 12, op.isREG(16|i32e)); }//-V524
+void cmovnl(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 13, op.isREG(16|i32e)); }//-V524
+void cmovnle(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 15, op.isREG(16|i32e)); }//-V524
+void cmovno(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 1, op.isREG(16|i32e)); }//-V524
+void cmovnp(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 11, op.isREG(16|i32e)); }//-V524
+void cmovns(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 9, op.isREG(16|i32e)); }//-V524
+void cmovnz(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 5, op.isREG(16|i32e)); }//-V524
+void cmovo(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 0, op.isREG(16|i32e)); }//-V524
+void cmovp(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 10, op.isREG(16|i32e)); }//-V524
+void cmovpe(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 10, op.isREG(16|i32e)); }//-V524
+void cmovpo(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 11, op.isREG(16|i32e)); }//-V524
+void cmovs(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 8, op.isREG(16|i32e)); }//-V524
+void cmovz(const Reg& reg, const Operand& op) { opRO(reg, op, T_0F, 0x40 | 4, op.isREG(16|i32e)); }//-V524
void cmp(const Operand& op, uint32_t imm) { opOI(op, imm, 0x38, 7); }
void cmp(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x38); }
void cmpeqpd(const Xmm& x, const Operand& op) { cmppd(x, op, 0); }
@@ -147,12 +147,12 @@ void cmpunordpd(const Xmm& x, const Operand& op) { cmppd(x, op, 3); }
void cmpunordps(const Xmm& x, const Operand& op) { cmpps(x, op, 3); }
void cmpunordsd(const Xmm& x, const Operand& op) { cmpsd(x, op, 3); }
void cmpunordss(const Xmm& x, const Operand& op) { cmpss(x, op, 3); }
-void cmpxchg(const Operand& op, const Reg& reg) { opRO(reg, op, op.getBit() == reg.getBit(), T_0F, 0xB0 | (reg.isBit(8) ? 0 : 1)); }
+void cmpxchg(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0xB0 | (reg.isBit(8) ? 0 : 1), op.getBit() == reg.getBit()); }
void cmpxchg8b(const Address& addr) { opMR(addr, Reg32(1), T_0F, 0xC7); }
void comisd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_66, 0x2F, isXMM_XMMorMEM); }
void comiss(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | 0, 0x2F, isXMM_XMMorMEM); }
void cpuid() { db(0x0F); db(0xA2); }
-void crc32(const Reg32e& reg, const Operand& op) { if (reg.isBit(32) && op.isBit(16)) db(0x66); opRO(reg, op, true, T_F2 | T_0F38, 0xF0 | (op.isBit(8) ? 0 : 1)); }
+void crc32(const Reg32e& reg, const Operand& op) { if (reg.isBit(32) && op.isBit(16)) db(0x66); opRO(reg, op, T_F2 | T_0F38, 0xF0 | (op.isBit(8) ? 0 : 1)); }
void cvtdq2pd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_F3, 0xE6, isXMM_XMMorMEM); }
void cvtdq2ps(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | 0, 0x5B, isXMM_XMMorMEM); }
void cvtpd2dq(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_F2, 0xE6, isXMM_XMMorMEM); }
@@ -537,7 +537,7 @@ void movntpd(const Address& addr, const Xmm& reg) { opMR(addr, Reg16(reg.getIdx(
void movntps(const Address& addr, const Xmm& xmm) { opMR(addr, Mmx(xmm.getIdx()), T_0F, 0x2B); }
void movntq(const Address& addr, const Mmx& mmx) { if (!mmx.isMMX()) XBYAK_THROW(ERR_BAD_COMBINATION) opMR(addr, mmx, T_0F, 0xE7); }
void movq(const Address& addr, const Mmx& mmx) { if (mmx.isXMM()) db(0x66); opMR(addr, mmx, T_0F, mmx.isXMM() ? 0xD6 : 0x7F); }
-void movq(const Mmx& mmx, const Operand& op) { if (mmx.isXMM()) db(0xF3); opRO(mmx, op, mmx.getKind() == op.getKind(), T_0F, mmx.isXMM() ? 0x7E : 0x6F); }
+void movq(const Mmx& mmx, const Operand& op) { if (mmx.isXMM()) db(0xF3); opRO(mmx, op, T_0F, mmx.isXMM() ? 0x7E : 0x6F, mmx.getKind() == op.getKind()); }
void movq2dq(const Xmm& xmm, const Mmx& mmx) { opRR(xmm, mmx, T_F3 | T_0F, 0xD6); }
void movsb() { db(0xA4); }
void movsd() { db(0xA5); }
@@ -1403,7 +1403,7 @@ void wait() { db(0x9B); }
void wbinvd() { db(0x0F); db(0x09); }
void wrmsr() { db(0x0F); db(0x30); }
void xabort(uint8_t imm) { db(0xC6); db(0xF8); db(imm); }
-void xadd(const Operand& op, const Reg& reg) { opRO(reg, op, op.getBit() == reg.getBit(), T_0F, 0xC0 | (reg.isBit(8) ? 0 : 1)); }
+void xadd(const Operand& op, const Reg& reg) { opRO(reg, op, T_0F, 0xC0 | (reg.isBit(8) ? 0 : 1), op.getBit() == reg.getBit()); }
void xbegin(uint32_t rel) { db(0xC7); db(0xF8); dd(rel); }
void xend() { db(0x0F); db(0x01); db(0xD5); }
void xgetbv() { db(0x0F); db(0x01); db(0xD0); }
@@ -1696,7 +1696,7 @@ void cmpxchg16b(const Address& addr) { opMR(addr, Reg64(1), T_0F, 0xC7); }
void fxrstor64(const Address& addr) { opMR(addr, Reg64(1), T_0F, 0xAE); }
void movq(const Reg64& reg, const Mmx& mmx) { if (mmx.isXMM()) db(0x66); opRR(mmx, reg, T_0F, 0x7E); }
void movq(const Mmx& mmx, const Reg64& reg) { if (mmx.isXMM()) db(0x66); opRR(mmx, reg, T_0F, 0x6E); }
-void movsxd(const Reg64& reg, const Operand& op) { if (!op.isBit(32)) XBYAK_THROW(ERR_BAD_COMBINATION) opRO(reg, op, true, 0, 0x63); }
+void movsxd(const Reg64& reg, const Operand& op) { if (!op.isBit(32)) XBYAK_THROW(ERR_BAD_COMBINATION) opRO(reg, op, 0, 0x63); }
void pextrq(const Operand& op, const Xmm& xmm, uint8_t imm) { if (!op.isREG(64) && !op.isMEM()) XBYAK_THROW(ERR_BAD_COMBINATION) opSSE(Reg64(xmm.getIdx()), op, T_66 | T_0F3A, 0x16, 0, imm); }
void pinsrq(const Xmm& xmm, const Operand& op, uint8_t imm) { if (!op.isREG(64) && !op.isMEM()) XBYAK_THROW(ERR_BAD_COMBINATION) opSSE(Reg64(xmm.getIdx()), op, T_66 | T_0F3A, 0x22, 0, imm); }
void senduipi(const Reg64& r) { opRR(Reg32(6), r.cvt32(), T_F3 | T_0F, 0xC7); }
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 03:33:34 +0000