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| author | MerryMage <[email protected]> | 2020-06-18 17:39:56 +0100 |
|---|---|---|
| committer | MerryMage <[email protected]> | 2020-06-18 17:59:44 +0100 |
| commit | 7402d38675d2a084593a13a26d2903331a2ddf7d (patch) | |
| tree | cb3525f9dcf8e10ad39e292ad05be079b5d89e14 | |
| parent | d34763242c8e37902a06bfdb3a2c42b32d3e1c24 (diff) | |
| download | dynarmic-7402d38675d2a084593a13a26d2903331a2ddf7d.tar.gz dynarmic-7402d38675d2a084593a13a26d2903331a2ddf7d.zip | |
test_arm_instructions: Add vclt.f32 (zero) test
| -rw-r--r-- | tests/A32/test_arm_instructions.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/A32/test_arm_instructions.cpp b/tests/A32/test_arm_instructions.cpp index 11b263f9..1aeb31bb 100644 --- a/tests/A32/test_arm_instructions.cpp +++ b/tests/A32/test_arm_instructions.cpp @@ -465,3 +465,23 @@ TEST_CASE("arm: PackedAbsDiffSumS8", "[arm][A32]") { REQUIRE(jit.Regs()[15] == 0x00000008); REQUIRE(jit.Cpsr() == 0xb0000010); } + +TEST_CASE("arm: vclt.f32 with zero", "[arm][A32][.]") { + ArmTestEnv test_env; + A32::Jit jit{GetUserConfig(&test_env)}; + test_env.code_mem = { + 0xf3b93628, // vclt.f32 d3, d24, #0 + 0xeafffffe, // b +#0 + }; + + jit.ExtRegs()[48] = 0x3a87d9f1; + jit.ExtRegs()[49] = 0x80796dc0; + + jit.SetCpsr(0x000001d0); // User-mode + + test_env.ticks_left = 2; + jit.Run(); + + REQUIRE(jit.ExtRegs()[6] == 0x00000000); + REQUIRE(jit.ExtRegs()[7] == 0x00000000); +} |