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| author | Merry <[email protected]> | 2022-11-08 20:05:58 +0000 |
|---|---|---|
| committer | Merry <[email protected]> | 2022-11-08 21:40:45 +0000 |
| commit | 7dbd87ba2d1549b60f5e3d94d2692a15488fdea8 (patch) | |
| tree | b9cf5ce5bd69cf56c89f2d33ac10a841211a916a /tests/A32 | |
| parent | 282bd3ad5c63ffcdc718a910f8fe333418146d5d (diff) | |
| download | dynarmic-7dbd87ba2d1549b60f5e3d94d2692a15488fdea8.tar.gz dynarmic-7dbd87ba2d1549b60f5e3d94d2692a15488fdea8.zip | |
backend/arm64/a32_address_space: Terminate early if halted prior to execution beginning
Diffstat (limited to 'tests/A32')
| -rw-r--r-- | tests/A32/test_arm_instructions.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/A32/test_arm_instructions.cpp b/tests/A32/test_arm_instructions.cpp index 5976b6af..e1459264 100644 --- a/tests/A32/test_arm_instructions.cpp +++ b/tests/A32/test_arm_instructions.cpp @@ -239,6 +239,7 @@ TEST_CASE("arm: Test InvalidateCacheRange", "[arm][A32]") { test_env.ticks_left = 4; jit.Run(); + jit.Run(); REQUIRE(jit.Regs()[0] == 5); REQUIRE(jit.Regs()[1] == 7); |