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authorMerryMage <[email protected]>2019-07-27 19:54:57 +0100
committerMerryMage <[email protected]>2020-04-22 21:04:23 +0100
commitc7d20f3f2fcde764f24560631f1dcb0965419d3a (patch)
tree2d80b4f85264280c6e3e30a7d06259000b7059d9 /tests/A32
parent39ab7cb6434d6b7eaebd94177d78e71b6ca540e8 (diff)
downloaddynarmic-c7d20f3f2fcde764f24560631f1dcb0965419d3a.tar.gz
dynarmic-c7d20f3f2fcde764f24560631f1dcb0965419d3a.zip
fuzz_arm: Test MSR and MRS instructions against unicorn
* Add always_little_endian option to mach unicorn behavior. * Correct CPSR.Mode = Usermode
Diffstat (limited to 'tests/A32')
-rw-r--r--tests/A32/fuzz_arm.cpp8
1 files changed, 3 insertions, 5 deletions
diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp
index 7f9bcfa8..e94698b9 100644
--- a/tests/A32/fuzz_arm.cpp
+++ b/tests/A32/fuzz_arm.cpp
@@ -108,9 +108,6 @@ u32 GenRandomInst(u32 pc, bool is_last_inst) {
"arm_CPS", "arm_RFE", "arm_SRS",
// Undefined
"arm_UDF",
-
- // Behavior differs from Qemu
- "arm_MSR_reg", "arm_MSR_imm", "arm_MRS",
};
for (const auto& [fn, bitstring] : list) {
@@ -140,6 +137,7 @@ Dynarmic::A32::UserConfig GetUserConfig(ArmTestEnv& testenv) {
Dynarmic::A32::UserConfig user_config;
user_config.enable_fast_dispatch = false;
user_config.callbacks = &testenv;
+ user_config.always_little_endian = true;
return user_config;
}
@@ -287,7 +285,7 @@ TEST_CASE("A32: Single random instruction", "[arm]") {
instructions[0] = GenRandomInst(0, true);
const u32 start_address = 100;
- const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x13;
+ const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x10;
const u32 fpcr = RandomFpcr();
INFO("Instruction: 0x" << std::hex << instructions[0]);
@@ -319,7 +317,7 @@ TEST_CASE("A32: Small random block", "[arm]") {
instructions[4] = GenRandomInst(16, true);
const u32 start_address = 100;
- const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x13;
+ const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x10;
const u32 fpcr = RandomFpcr();
INFO("Instruction 1: 0x" << std::hex << instructions[0]);