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-rw-r--r--tests/A32/fuzz_arm.cpp10
-rw-r--r--tests/A32/fuzz_thumb.cpp108
-rw-r--r--tests/A32/test_thumb_instructions.cpp2
-rw-r--r--tests/A32/testenv.h5
-rw-r--r--tests/A64/fuzz_with_unicorn.cpp4
-rw-r--r--tests/A64/testenv.h5
-rw-r--r--tests/decoder_tests.cpp2
-rw-r--r--tests/fp/FPToFixed.cpp2
-rw-r--r--tests/fp/mantissa_util_tests.cpp4
-rw-r--r--tests/fp/unpacked_tests.cpp2
-rw-r--r--tests/fuzz_util.cpp2
-rw-r--r--tests/fuzz_util.h2
-rw-r--r--tests/print_info.cpp6
-rw-r--r--tests/rsqrt_test.cpp2
-rw-r--r--tests/unicorn_emu/a32_unicorn.cpp9
-rw-r--r--tests/unicorn_emu/a32_unicorn.h3
-rw-r--r--tests/unicorn_emu/a64_unicorn.cpp2
-rw-r--r--tests/unicorn_emu/a64_unicorn.h3
18 files changed, 90 insertions, 83 deletions
diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp
index ccc3d46b..bd53af15 100644
--- a/tests/A32/fuzz_arm.cpp
+++ b/tests/A32/fuzz_arm.cpp
@@ -11,16 +11,18 @@
#include <vector>
#include <catch2/catch.hpp>
+#include <mcl/bit/bit_count.hpp>
+#include <mcl/bit/swap.hpp>
+#include <mcl/scope_exit.hpp>
+#include <mcl/stdint.hpp>
#include "../fuzz_util.h"
#include "../rand_int.h"
#include "../unicorn_emu/a32_unicorn.h"
#include "./testenv.h"
-#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/llvm_disassemble.h"
-#include "dynarmic/common/scope_exit.h"
#include "dynarmic/frontend/A32/ITState.h"
#include "dynarmic/frontend/A32/a32_location_descriptor.h"
#include "dynarmic/frontend/A32/a32_types.h"
@@ -255,7 +257,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
const u32 inst = instructions.generators[index].Generate();
const bool is_four_bytes = (inst >> 16) != 0;
- if (ShouldTestInst(is_four_bytes ? Common::SwapHalves32(inst) : inst, pc, true, is_last_inst, it_state)) {
+ if (ShouldTestInst(is_four_bytes ? mcl::bit::swap_halves_32(inst) : inst, pc, true, is_last_inst, it_state)) {
if (is_four_bytes)
return {static_cast<u16>(inst >> 16), static_cast<u16>(inst)};
return {static_cast<u16>(inst)};
@@ -625,7 +627,7 @@ TEST_CASE("A32: Test thumb IT instruction", "[thumb]") {
A32::ITState it_state = [&] {
while (true) {
const u16 imm8 = RandInt<u16>(0, 0xFF);
- if (Common::Bits<0, 3>(imm8) == 0b0000 || Common::Bits<4, 7>(imm8) == 0b1111 || (Common::Bits<4, 7>(imm8) == 0b1110 && Common::BitCount(Common::Bits<0, 3>(imm8)) != 1)) {
+ if (mcl::bit::get_bits<0, 3>(imm8) == 0b0000 || mcl::bit::get_bits<4, 7>(imm8) == 0b1111 || (mcl::bit::get_bits<4, 7>(imm8) == 0b1110 && mcl::bit::count_ones(mcl::bit::get_bits<0, 3>(imm8)) != 1)) {
continue;
}
instructions.push_back(0b1011111100000000 | imm8);
diff --git a/tests/A32/fuzz_thumb.cpp b/tests/A32/fuzz_thumb.cpp
index a7b04a57..d412b97e 100644
--- a/tests/A32/fuzz_thumb.cpp
+++ b/tests/A32/fuzz_thumb.cpp
@@ -13,12 +13,12 @@
#include <tuple>
#include <catch2/catch.hpp>
+#include <mcl/bit/bit_field.hpp>
+#include <mcl/stdint.hpp>
#include "../rand_int.h"
#include "../unicorn_emu/a32_unicorn.h"
#include "./testenv.h"
-#include "dynarmic/common/bit_util.h"
-#include "dynarmic/common/common_types.h"
#include "dynarmic/frontend/A32/FPSCR.h"
#include "dynarmic/frontend/A32/PSR.h"
#include "dynarmic/frontend/A32/a32_location_descriptor.h"
@@ -236,8 +236,8 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to
for (size_t i = 0; i < instruction_count; i++) {
const auto instruction = instruction_generator();
- const auto first_halfword = static_cast<u16>(Common::Bits<0, 15>(instruction));
- const auto second_halfword = static_cast<u16>(Common::Bits<16, 31>(instruction));
+ const auto first_halfword = static_cast<u16>(mcl::bit::get_bits<0, 15>(instruction));
+ const auto second_halfword = static_cast<u16>(mcl::bit::get_bits<16, 31>(instruction));
test_env.code_mem[i * 2 + 0] = second_halfword;
test_env.code_mem[i * 2 + 1] = first_halfword;
@@ -249,39 +249,39 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to
TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") {
const std::array instructions = {
- ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
- ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
- ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
- ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
- ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
- ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
- ThumbInstGen("010000ooooxxxxxx"), // Data Processing
- ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
- ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
- [](u32 inst) { return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
- ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
- [](u32 inst) { return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
- ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
- ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
- ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
- ThumbInstGen("1011101000xxxxxx"), // REV
- ThumbInstGen("1011101001xxxxxx"), // REV16
- ThumbInstGen("1011101011xxxxxx"), // REVSH
- ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
- ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
- ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
- ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
- ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
- ThumbInstGen("1011010xxxxxxxxx", // PUSH
- [](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
- ThumbInstGen("10111100xxxxxxxx", // POP (P = 0)
- [](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
- ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA
+ ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
+ ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
+ ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
+ ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
+ ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
+ ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
+ ThumbInstGen("010000ooooxxxxxx"), // Data Processing
+ ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
+ ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
+ [](u32 inst) { return mcl::bit::get_bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
+ ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
+ [](u32 inst) { return mcl::bit::get_bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
+ ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
+ ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
+ ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
+ ThumbInstGen("1011101000xxxxxx"), // REV
+ ThumbInstGen("1011101001xxxxxx"), // REV16
+ ThumbInstGen("1011101011xxxxxx"), // REVSH
+ ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
+ ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
+ ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
+ ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
+ ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
+ ThumbInstGen("1011010xxxxxxxxx", // PUSH
+ [](u32 inst) { return mcl::bit::get_bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
+ ThumbInstGen("10111100xxxxxxxx", // POP (P = 0)
+ [](u32 inst) { return mcl::bit::get_bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
+ ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA
[](u32 inst) {
// Ensure that the architecturally undefined case of
// the base register being within the list isn't hit.
- const u32 rn = Common::Bits<8, 10>(inst);
- return (inst & (1U << rn)) == 0 && Common::Bits<0, 7>(inst) != 0;
+ const u32 rn = mcl::bit::get_bits<8, 10>(inst);
+ return (inst & (1U << rn)) == 0 && mcl::bit::get_bits<0, 7>(inst) != 0;
}),
// TODO: We should properly test against swapped
// endianness cases, however Unicorn doesn't
@@ -325,7 +325,7 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16
#if 0
ThumbInstGen("01000111xmmmm000", // BLX/BX
[](u32 inst){
- const u32 Rm = Common::Bits<3, 6>(inst);
+ const u32 Rm = mcl::bit::get_bits<3, 6>(inst);
return Rm != 15;
}),
#endif
@@ -335,7 +335,7 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16
ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers)
ThumbInstGen("1101ccccxxxxxxxx", // B<cond>
[](u32 inst) {
- const u32 c = Common::Bits<9, 12>(inst);
+ const u32 c = mcl::bit::get_bits<9, 12>(inst);
return c < 0b1110; // Don't want SWI or undefined instructions.
}),
ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ
@@ -360,18 +360,18 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16
TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
const auto three_reg_not_r15 = [](u32 inst) {
- const auto d = Common::Bits<8, 11>(inst);
- const auto m = Common::Bits<0, 3>(inst);
- const auto n = Common::Bits<16, 19>(inst);
+ const auto d = mcl::bit::get_bits<8, 11>(inst);
+ const auto m = mcl::bit::get_bits<0, 3>(inst);
+ const auto n = mcl::bit::get_bits<16, 19>(inst);
return d != 15 && m != 15 && n != 15;
};
const std::array instructions = {
ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ
[](u32 inst) {
- const auto d = Common::Bits<8, 11>(inst);
- const auto m = Common::Bits<0, 3>(inst);
- const auto n = Common::Bits<16, 19>(inst);
+ const auto d = mcl::bit::get_bits<8, 11>(inst);
+ const auto m = mcl::bit::get_bits<0, 3>(inst);
+ const auto n = mcl::bit::get_bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD
@@ -396,30 +396,30 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT
[](u32 inst) {
- const auto d = Common::Bits<8, 11>(inst);
- const auto m = Common::Bits<0, 3>(inst);
- const auto n = Common::Bits<16, 19>(inst);
+ const auto d = mcl::bit::get_bits<8, 11>(inst);
+ const auto m = mcl::bit::get_bits<0, 3>(inst);
+ const auto n = mcl::bit::get_bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV
[](u32 inst) {
- const auto d = Common::Bits<8, 11>(inst);
- const auto m = Common::Bits<0, 3>(inst);
- const auto n = Common::Bits<16, 19>(inst);
+ const auto d = mcl::bit::get_bits<8, 11>(inst);
+ const auto m = mcl::bit::get_bits<0, 3>(inst);
+ const auto n = mcl::bit::get_bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16
[](u32 inst) {
- const auto d = Common::Bits<8, 11>(inst);
- const auto m = Common::Bits<0, 3>(inst);
- const auto n = Common::Bits<16, 19>(inst);
+ const auto d = mcl::bit::get_bits<8, 11>(inst);
+ const auto m = mcl::bit::get_bits<0, 3>(inst);
+ const auto n = mcl::bit::get_bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH
[](u32 inst) {
- const auto d = Common::Bits<8, 11>(inst);
- const auto m = Common::Bits<0, 3>(inst);
- const auto n = Common::Bits<16, 19>(inst);
+ const auto d = mcl::bit::get_bits<8, 11>(inst);
+ const auto m = mcl::bit::get_bits<0, 3>(inst);
+ const auto n = mcl::bit::get_bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8
diff --git a/tests/A32/test_thumb_instructions.cpp b/tests/A32/test_thumb_instructions.cpp
index 734836a6..c403f8bb 100644
--- a/tests/A32/test_thumb_instructions.cpp
+++ b/tests/A32/test_thumb_instructions.cpp
@@ -4,9 +4,9 @@
*/
#include <catch2/catch.hpp>
+#include <mcl/stdint.hpp>
#include "./testenv.h"
-#include "dynarmic/common/common_types.h"
#include "dynarmic/interface/A32/a32.h"
static Dynarmic::A32::UserConfig GetUserConfig(ThumbTestEnv* testenv) {
diff --git a/tests/A32/testenv.h b/tests/A32/testenv.h
index 68538ba2..ac7921ec 100644
--- a/tests/A32/testenv.h
+++ b/tests/A32/testenv.h
@@ -11,8 +11,9 @@
#include <string>
#include <vector>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <mcl/assert.hpp>
+#include <mcl/stdint.hpp>
+
#include "dynarmic/interface/A32/a32.h"
template<typename InstructionType_, u32 infinite_loop_u32>
diff --git a/tests/A64/fuzz_with_unicorn.cpp b/tests/A64/fuzz_with_unicorn.cpp
index 433f8ca9..0307751c 100644
--- a/tests/A64/fuzz_with_unicorn.cpp
+++ b/tests/A64/fuzz_with_unicorn.cpp
@@ -9,16 +9,16 @@
#include <vector>
#include <catch2/catch.hpp>
+#include <mcl/scope_exit.hpp>
+#include <mcl/stdint.hpp>
#include "../fuzz_util.h"
#include "../rand_int.h"
#include "../unicorn_emu/a64_unicorn.h"
#include "./testenv.h"
-#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/llvm_disassemble.h"
-#include "dynarmic/common/scope_exit.h"
#include "dynarmic/frontend/A64/a64_location_descriptor.h"
#include "dynarmic/frontend/A64/a64_types.h"
#include "dynarmic/frontend/A64/decoder/a64.h"
diff --git a/tests/A64/testenv.h b/tests/A64/testenv.h
index d18797f2..596d0114 100644
--- a/tests/A64/testenv.h
+++ b/tests/A64/testenv.h
@@ -8,8 +8,9 @@
#include <array>
#include <map>
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/common_types.h"
+#include <mcl/assert.hpp>
+#include <mcl/stdint.hpp>
+
#include "dynarmic/interface/A64/a64.h"
using Vector = Dynarmic::A64::Vector;
diff --git a/tests/decoder_tests.cpp b/tests/decoder_tests.cpp
index b4b12273..519d2b17 100644
--- a/tests/decoder_tests.cpp
+++ b/tests/decoder_tests.cpp
@@ -8,8 +8,8 @@
#include <iostream>
#include <catch2/catch.hpp>
+#include <mcl/assert.hpp>
-#include "dynarmic/common/assert.h"
#include "dynarmic/frontend/A32/decoder/asimd.h"
#include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h"
#include "dynarmic/interface/A32/config.h"
diff --git a/tests/fp/FPToFixed.cpp b/tests/fp/FPToFixed.cpp
index 354ab483..9375003f 100644
--- a/tests/fp/FPToFixed.cpp
+++ b/tests/fp/FPToFixed.cpp
@@ -7,9 +7,9 @@
#include <vector>
#include <catch2/catch.hpp>
+#include <mcl/stdint.hpp>
#include "../rand_int.h"
-#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/fp/op.h"
diff --git a/tests/fp/mantissa_util_tests.cpp b/tests/fp/mantissa_util_tests.cpp
index ce833ff6..76311f1f 100644
--- a/tests/fp/mantissa_util_tests.cpp
+++ b/tests/fp/mantissa_util_tests.cpp
@@ -7,9 +7,9 @@
#include <vector>
#include <catch2/catch.hpp>
+#include <mcl/stdint.hpp>
#include "../rand_int.h"
-#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/mantissa_util.h"
#include "dynarmic/common/safe_ops.h"
@@ -37,7 +37,7 @@ TEST_CASE("ResidualErrorOnRightShift", "[fp]") {
TEST_CASE("ResidualErrorOnRightShift Randomized", "[fp]") {
for (size_t test = 0; test < 100000; test++) {
- const u64 mantissa = Common::SignExtend<32, u64>(RandInt<u32>(0, 0xFFFFFFFF));
+ const u64 mantissa = mcl::bit::sign_extend<32, u64>(RandInt<u32>(0, 0xFFFFFFFF));
const int shift = RandInt<int>(-60, 60);
const ResidualError result = ResidualErrorOnRightShift(mantissa, shift);
diff --git a/tests/fp/unpacked_tests.cpp b/tests/fp/unpacked_tests.cpp
index d201e7ec..d61f514f 100644
--- a/tests/fp/unpacked_tests.cpp
+++ b/tests/fp/unpacked_tests.cpp
@@ -7,9 +7,9 @@
#include <vector>
#include <catch2/catch.hpp>
+#include <mcl/stdint.hpp>
#include "../rand_int.h"
-#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/fp/unpacked.h"
diff --git a/tests/fuzz_util.cpp b/tests/fuzz_util.cpp
index 1de6c29f..12dc850b 100644
--- a/tests/fuzz_util.cpp
+++ b/tests/fuzz_util.cpp
@@ -9,9 +9,9 @@
#include <fmt/format.h>
#include <fmt/ostream.h>
+#include <mcl/assert.hpp>
#include "./rand_int.h"
-#include "dynarmic/common/assert.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/rounding_mode.h"
diff --git a/tests/fuzz_util.h b/tests/fuzz_util.h
index 04334272..95303077 100644
--- a/tests/fuzz_util.h
+++ b/tests/fuzz_util.h
@@ -8,7 +8,7 @@
#include <array>
#include <iosfwd>
-#include "dynarmic/common/common_types.h"
+#include <mcl/stdint.hpp>
using Vector = std::array<u64, 2>;
diff --git a/tests/print_info.cpp b/tests/print_info.cpp
index c20ac371..d7978fd8 100644
--- a/tests/print_info.cpp
+++ b/tests/print_info.cpp
@@ -14,9 +14,9 @@
#include <fmt/format.h>
#include <fmt/ostream.h>
+#include <mcl/bit/swap.hpp>
+#include <mcl/stdint.hpp>
-#include "dynarmic/common/bit_util.h"
-#include "dynarmic/common/common_types.h"
#include "dynarmic/common/llvm_disassemble.h"
#include "dynarmic/frontend/A32/a32_location_descriptor.h"
#include "dynarmic/frontend/A32/decoder/arm.h"
@@ -98,7 +98,7 @@ void PrintA64Instruction(u32 instruction) {
void PrintThumbInstruction(u32 instruction) {
const size_t inst_size = (instruction >> 16) == 0 ? 2 : 4;
if (inst_size == 4)
- instruction = Common::SwapHalves32(instruction);
+ instruction = mcl::bit::swap_halves_32(instruction);
fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch32(true, 0, (u8*)&instruction, inst_size));
diff --git a/tests/rsqrt_test.cpp b/tests/rsqrt_test.cpp
index f367da87..cb49ca0c 100644
--- a/tests/rsqrt_test.cpp
+++ b/tests/rsqrt_test.cpp
@@ -5,8 +5,8 @@
#include <catch2/catch.hpp>
#include <fmt/printf.h>
+#include <mcl/stdint.hpp>
-#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/fp/op/FPRSqrtEstimate.h"
diff --git a/tests/unicorn_emu/a32_unicorn.cpp b/tests/unicorn_emu/a32_unicorn.cpp
index d9a68662..f3ffa0da 100644
--- a/tests/unicorn_emu/a32_unicorn.cpp
+++ b/tests/unicorn_emu/a32_unicorn.cpp
@@ -7,9 +7,10 @@
#include <type_traits>
+#include <mcl/assert.hpp>
+#include <mcl/bit/bit_field.hpp>
+
#include "../A32/testenv.h"
-#include "dynarmic/common/assert.h"
-#include "dynarmic/common/bit_util.h"
#define CHECKED(expr) \
do { \
@@ -60,7 +61,7 @@ void A32Unicorn<TestEnvironment>::Run() {
}
}
- const bool T = Dynarmic::Common::Bit<5>(GetCpsr());
+ const bool T = mcl::bit::get_bit<5>(GetCpsr());
const u32 new_pc = GetPC() | (T ? 1 : 0);
SetPC(new_pc);
}
@@ -262,7 +263,7 @@ void A32Unicorn<TestEnvironment>::InterruptHook(uc_engine* /*uc*/, u32 int_numbe
auto* this_ = static_cast<A32Unicorn*>(user_data);
u32 esr = 0;
- //CHECKED(uc_reg_read(uc, UC_ARM_REG_ESR, &esr));
+ // CHECKED(uc_reg_read(uc, UC_ARM_REG_ESR, &esr));
auto ec = esr >> 26;
auto iss = esr & 0xFFFFFF;
diff --git a/tests/unicorn_emu/a32_unicorn.h b/tests/unicorn_emu/a32_unicorn.h
index 1cf06a02..d4fe3c41 100644
--- a/tests/unicorn_emu/a32_unicorn.h
+++ b/tests/unicorn_emu/a32_unicorn.h
@@ -16,8 +16,9 @@
# include <unicorn/unicorn.h>
#endif
+#include <mcl/stdint.hpp>
+
#include "../A32/testenv.h"
-#include "dynarmic/common/common_types.h"
namespace Unicorn::A32 {
static constexpr size_t num_gprs = 16;
diff --git a/tests/unicorn_emu/a64_unicorn.cpp b/tests/unicorn_emu/a64_unicorn.cpp
index 583e04d9..f4e14b25 100644
--- a/tests/unicorn_emu/a64_unicorn.cpp
+++ b/tests/unicorn_emu/a64_unicorn.cpp
@@ -5,7 +5,7 @@
#include "./a64_unicorn.h"
-#include "dynarmic/common/assert.h"
+#include <mcl/assert.hpp>
#define CHECKED(expr) \
do { \
diff --git a/tests/unicorn_emu/a64_unicorn.h b/tests/unicorn_emu/a64_unicorn.h
index 580c88a0..57759605 100644
--- a/tests/unicorn_emu/a64_unicorn.h
+++ b/tests/unicorn_emu/a64_unicorn.h
@@ -16,8 +16,9 @@
# include <unicorn/unicorn.h>
#endif
+#include <mcl/stdint.hpp>
+
#include "../A64/testenv.h"
-#include "dynarmic/common/common_types.h"
class A64Unicorn final {
public:
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 12:04:09 +0000