aboutsummaryrefslogtreecommitdiffhomepage
path: root/src
diff options
context:
space:
mode:
authorAyke van Laethem <[email protected]>2022-02-05 13:27:50 +0100
committerRon Evans <[email protected]>2022-02-13 07:34:40 +0100
commit262291a80a051d056af4453705641395ff722de3 (patch)
tree4729bb7da999b6de0f0fdf91f61ad08e100e449d /src
parentcdd267fa10370e294480fa203af1fc1cd91b47fa (diff)
downloadtinygo-262291a80a051d056af4453705641395ff722de3.tar.gz
tinygo-262291a80a051d056af4453705641395ff722de3.zip
rp2040: fix incorrect inline assembly
The register r0 was used unconditionally. This is a bug: the compiler doesn't know it is clobbered and might consider it alive across the inline assembly expression. The fix is simple. It could probably be optimized, but this should at least fix the bug.
Diffstat (limited to 'src')
-rw-r--r--src/machine/machine_rp2040_clocks.go17
1 files changed, 7 insertions, 10 deletions
diff --git a/src/machine/machine_rp2040_clocks.go b/src/machine/machine_rp2040_clocks.go
index 3a0c714a7..f9d533a07 100644
--- a/src/machine/machine_rp2040_clocks.go
+++ b/src/machine/machine_rp2040_clocks.go
@@ -149,16 +149,13 @@ func (clk *clock) configure(src, auxsrc, srcFreq, freq uint32) {
// Note XOSC_COUNT is not helpful here because XOSC is not
// necessarily running, nor is timer... so, 3 cycles per loop:
delayCyc := configuredFreq[clkSys]/configuredFreq[clk.cix] + 1
- arm.AsmFull(
- `
- ldr r0, {cyc}
- 1:
- subs r0, #1
- bne 1b
- `,
- map[string]interface{}{
- "cyc": &delayCyc,
- })
+ for delayCyc != 0 {
+ // This could be done more efficiently but TinyGo inline
+ // assembly is not yet capable enough to express that. In the
+ // meantime, this forces at least 3 cycles per loop.
+ delayCyc--
+ arm.Asm("nop\nnop\nnop")
+ }
}
}