blob: 1155d553eba1e330a8420e01ceace69066f19822 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
|
// +build tinygo.riscv,virt,qemu
package runtime
import (
"device/riscv"
"runtime/volatile"
"unsafe"
)
// This file implements the VirtIO RISC-V interface implemented in QEMU, which
// is an interface designed for emulation.
type timeUnit int64
const tickMicros = 1
var timestamp timeUnit
func postinit() {}
//export main
func main() {
preinit()
run()
abort()
}
const asyncScheduler = false
func sleepTicks(d timeUnit) {
// TODO: actually sleep here for the given time.
timestamp += d
}
func ticks() timeUnit {
return timestamp
}
// Memory-mapped I/O as defined by QEMU.
// Source: https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c
// Technically this is an implementation detail but hopefully they won't change
// the memory-mapped I/O registers.
var (
// UART0 output register.
stdoutWrite = (*volatile.Register8)(unsafe.Pointer(uintptr(0x10000000)))
// SiFive test finisher
testFinisher = (*volatile.Register16)(unsafe.Pointer(uintptr(0x100000)))
)
func putchar(c byte) {
stdoutWrite.Set(uint8(c))
}
func abort() {
// Make sure the QEMU process exits.
testFinisher.Set(0x5555) // FINISHER_PASS
// Lock up forever (as a fallback).
for {
riscv.Asm("wfi")
}
}
|