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| author | Andrzej Janik <[email protected]> | 2024-05-06 00:28:49 +0200 |
|---|---|---|
| committer | GitHub <[email protected]> | 2024-05-06 00:28:49 +0200 |
| commit | 27c0e136777a2db49dbb0caa888d561819230493 (patch) | |
| tree | 06a395462378d64ed504f3ec0a1b877de12ba98c /ptx/src/test/spirv_run/bra.ll | |
| parent | bdc652f9ebcac9a79849eeee84a391a4ac107913 (diff) | |
| download | ZLUDA-27c0e136777a2db49dbb0caa888d561819230493.tar.gz ZLUDA-27c0e136777a2db49dbb0caa888d561819230493.zip | |
Minor codegen improvements (#225)
Diffstat (limited to 'ptx/src/test/spirv_run/bra.ll')
| -rw-r--r-- | ptx/src/test/spirv_run/bra.ll | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/ptx/src/test/spirv_run/bra.ll b/ptx/src/test/spirv_run/bra.ll index 6d62cca..4173392 100644 --- a/ptx/src/test/spirv_run/bra.ll +++ b/ptx/src/test/spirv_run/bra.ll @@ -2,13 +2,15 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3 target triple = "amdgcn-amd-amdhsa" define protected amdgpu_kernel void @bra(ptr addrspace(4) byref(i64) %"24", ptr addrspace(4) byref(i64) %"25") #0 { -"28": %"11" = alloca i1, align 1, addrspace(5) - store i1 false, ptr addrspace(5) %"11", align 1 %"7" = alloca i64, align 8, addrspace(5) %"8" = alloca i64, align 8, addrspace(5) %"9" = alloca i64, align 8, addrspace(5) %"10" = alloca i64, align 8, addrspace(5) + br label %1 + +1: ; preds = %0 + store i1 false, ptr addrspace(5) %"11", align 1 %"12" = load i64, ptr addrspace(4) %"24", align 8 store i64 %"12", ptr addrspace(5) %"7", align 8 %"13" = load i64, ptr addrspace(4) %"25", align 8 @@ -19,19 +21,19 @@ define protected amdgpu_kernel void @bra(ptr addrspace(4) byref(i64) %"24", ptr store i64 %"14", ptr addrspace(5) %"9", align 8 br label %"4" -"4": ; preds = %"28" +"4": ; preds = %1 %"17" = load i64, ptr addrspace(5) %"9", align 8 %"16" = add i64 %"17", 1 store i64 %"16", ptr addrspace(5) %"10", align 8 br label %"6" -0: ; No predecessors! +"5": ; No predecessors! %"19" = load i64, ptr addrspace(5) %"9", align 8 %"18" = add i64 %"19", 2 store i64 %"18", ptr addrspace(5) %"10", align 8 br label %"6" -"6": ; preds = %0, %"4" +"6": ; preds = %"5", %"4" %"20" = load i64, ptr addrspace(5) %"8", align 8 %"21" = load i64, ptr addrspace(5) %"10", align 8 %"27" = inttoptr i64 %"20" to ptr |