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| author | Andrzej Janik <[email protected]> | 2024-05-06 00:28:49 +0200 |
|---|---|---|
| committer | GitHub <[email protected]> | 2024-05-06 00:28:49 +0200 |
| commit | 27c0e136777a2db49dbb0caa888d561819230493 (patch) | |
| tree | 06a395462378d64ed504f3ec0a1b877de12ba98c /ptx/src/test/spirv_run/ld_st_implicit.ll | |
| parent | bdc652f9ebcac9a79849eeee84a391a4ac107913 (diff) | |
| download | ZLUDA-27c0e136777a2db49dbb0caa888d561819230493.tar.gz ZLUDA-27c0e136777a2db49dbb0caa888d561819230493.zip | |
Minor codegen improvements (#225)
Diffstat (limited to 'ptx/src/test/spirv_run/ld_st_implicit.ll')
| -rw-r--r-- | ptx/src/test/spirv_run/ld_st_implicit.ll | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/ptx/src/test/spirv_run/ld_st_implicit.ll b/ptx/src/test/spirv_run/ld_st_implicit.ll index 3ec1474..71baa92 100644 --- a/ptx/src/test/spirv_run/ld_st_implicit.ll +++ b/ptx/src/test/spirv_run/ld_st_implicit.ll @@ -2,31 +2,33 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3 target triple = "amdgcn-amd-amdhsa" define protected amdgpu_kernel void @ld_st_implicit(ptr addrspace(4) byref(i64) %"16", ptr addrspace(4) byref(i64) %"17") #0 { -"22": %"7" = alloca i1, align 1, addrspace(5) - store i1 false, ptr addrspace(5) %"7", align 1 %"4" = alloca i64, align 8, addrspace(5) %"5" = alloca i64, align 8, addrspace(5) %"6" = alloca i64, align 8, addrspace(5) + %1 = alloca i64, align 8, addrspace(5) + br label %2 + +2: ; preds = %0 + store i1 false, ptr addrspace(5) %"7", align 1 %"8" = load i64, ptr addrspace(4) %"16", align 8 store i64 %"8", ptr addrspace(5) %"4", align 8 %"9" = load i64, ptr addrspace(4) %"17", align 8 store i64 %"9", ptr addrspace(5) %"5", align 8 - %0 = alloca i64, align 8, addrspace(5) - store i64 81985529216486895, ptr addrspace(5) %0, align 8 - %"10" = load i64, ptr addrspace(5) %0, align 8 + store i64 81985529216486895, ptr addrspace(5) %1, align 8 + %"10" = load i64, ptr addrspace(5) %1, align 8 store i64 %"10", ptr addrspace(5) %"6", align 8 %"12" = load i64, ptr addrspace(5) %"4", align 8 %"19" = inttoptr i64 %"12" to ptr addrspace(1) %"18" = load float, ptr addrspace(1) %"19", align 4 - %"23" = bitcast float %"18" to i32 - %"11" = zext i32 %"23" to i64 + %"22" = bitcast float %"18" to i32 + %"11" = zext i32 %"22" to i64 store i64 %"11", ptr addrspace(5) %"6", align 8 %"13" = load i64, ptr addrspace(5) %"5", align 8 %"14" = load i64, ptr addrspace(5) %"6", align 8 %"20" = inttoptr i64 %"13" to ptr addrspace(1) - %"25" = trunc i64 %"14" to i32 - %"21" = bitcast i32 %"25" to float + %"24" = trunc i64 %"14" to i32 + %"21" = bitcast i32 %"24" to float store float %"21", ptr addrspace(1) %"20", align 4 ret void } |