diff options
| -rw-r--r-- | src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp b/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp index 7787b4bb..ff9bc462 100644 --- a/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp +++ b/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp @@ -248,4 +248,14 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx, as.SW(Xscratch0, offsetof(A32JitState, cpsr_nzcv), Xstate); } +template<> +void EmitIR<IR::Opcode::A32SetCpsrNZCV>(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + + auto Xnzcv = ctx.reg_alloc.ReadX(args[0]); + RegAlloc::Realize(Xnzcv); + + as.SW(Xnzcv, offsetof(A32JitState, cpsr_nzcv), Xstate); +} + } // namespace Dynarmic::Backend::RV64 |