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| author | Yang Liu <[email protected]> | 2024-02-17 18:22:24 +0800 |
|---|---|---|
| committer | Merry <[email protected]> | 2024-03-02 19:38:46 +0000 |
| commit | 208acb30260c6221b7684993cd9a253c4e8b9606 (patch) | |
| tree | 09d5ba3757a4bfb89fe2a70e7f63e2ead9e6c29c | |
| parent | 09c6f22da9154065e8523dd984bca22222372be4 (diff) | |
| download | dynarmic-208acb30260c6221b7684993cd9a253c4e8b9606.tar.gz dynarmic-208acb30260c6221b7684993cd9a253c4e8b9606.zip | |
backend/rv64: Implement A32SetCpsrNZCV
| -rw-r--r-- | src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp b/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp index 7787b4bb..ff9bc462 100644 --- a/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp +++ b/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp @@ -248,4 +248,14 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(biscuit::Assembler& as, EmitContext& ctx, as.SW(Xscratch0, offsetof(A32JitState, cpsr_nzcv), Xstate); } +template<> +void EmitIR<IR::Opcode::A32SetCpsrNZCV>(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + + auto Xnzcv = ctx.reg_alloc.ReadX(args[0]); + RegAlloc::Realize(Xnzcv); + + as.SW(Xnzcv, offsetof(A32JitState, cpsr_nzcv), Xstate); +} + } // namespace Dynarmic::Backend::RV64 |