rp2350 cleanup: unexport internal USB and clock package variable, consts and typesrp2350-cleanup

1 files changed, 27 insertions, 27 deletions

diff --git a/src/machine/machine_rp2_clocks.go b/src/machine/machine_rp2_clocks.go
index ad2c6517f..cc152a7f8 100644
--- a/src/machine/machine_rp2_clocks.go
+++ b/src/machine/machine_rp2_clocks.go
@@ -41,7 +41,7 @@ type fc struct {
 
 var clocks = (*clocksType)(unsafe.Pointer(rp.CLOCKS))
 
-var configuredFreq [NumClocks]uint32
+var configuredFreq [numClocks]uint32
 
 type clock struct {
 	*clockType
@@ -68,7 +68,7 @@ func (clks *clocksType) clock(cix clockIndex) clock {
 //
 // Not all clocks have both types of mux.
 func (clk *clock) hasGlitchlessMux() bool {
-	return clk.cix == ClkSys || clk.cix == ClkRef
+	return clk.cix == clkSys || clk.cix == clkRef
 }
 
 // configure configures the clock by selecting the main clock source src
@@ -80,7 +80,7 @@ func (clk *clock) configure(src, auxsrc, srcFreq, freq uint32) {
 		panic("clock frequency cannot be greater than source frequency")
 	}
 
-	div := CalcClockDiv(srcFreq, freq)
+	div := calcClockDiv(srcFreq, freq)
 
 	// If increasing divisor, set divisor before source. Otherwise set source
 	// before divisor. This avoids a momentary overspeed when e.g. switching
@@ -99,16 +99,16 @@ func (clk *clock) configure(src, auxsrc, srcFreq, freq uint32) {
 	} else
 	// If no glitchless mux, cleanly stop the clock to avoid glitches
 	// propagating when changing aux mux. Note it would be a really bad idea
-	// to do this on one of the glitchless clocks (ClkSys, ClkRef).
+	// to do this on one of the glitchless clocks (clkSys, clkRef).
 	{
-		// Disable clock. On ClkRef and ClkSys this does nothing,
+		// Disable clock. On clkRef and ClkSys this does nothing,
 		// all other clocks have the ENABLE bit in the same position.
 		clk.ctrl.ClearBits(rp.CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Msk)
 		if configuredFreq[clk.cix] > 0 {
 			// Delay for 3 cycles of the target clock, for ENABLE propagation.
 			// Note XOSC_COUNT is not helpful here because XOSC is not
 			// necessarily running, nor is timer... so, 3 cycles per loop:
-			delayCyc := configuredFreq[ClkSys]/configuredFreq[clk.cix] + 1
+			delayCyc := configuredFreq[clkSys]/configuredFreq[clk.cix] + 1
 			for delayCyc != 0 {
 				// This could be done more efficiently but TinyGo inline
 				// assembly is not yet capable enough to express that. In the
@@ -130,7 +130,7 @@ func (clk *clock) configure(src, auxsrc, srcFreq, freq uint32) {
 		}
 	}
 
-	// Enable clock. On ClkRef and ClkSys this does nothing,
+	// Enable clock. On clkRef and clkSys this does nothing,
 	// all other clocks have the ENABLE bit in the same position.
 	clk.ctrl.SetBits(rp.CLOCKS_CLK_GPOUT0_CTRL_ENABLE)
 
@@ -157,12 +157,12 @@ func (clks *clocksType) init() {
 	xosc.init()
 
 	// Before we touch PLLs, switch sys and ref cleanly away from their aux sources.
-	clks.clk[ClkSys].ctrl.ClearBits(rp.CLOCKS_CLK_SYS_CTRL_SRC_Msk)
-	for !clks.clk[ClkSys].selected.HasBits(0x1) {
+	clks.clk[clkSys].ctrl.ClearBits(rp.CLOCKS_CLK_SYS_CTRL_SRC_Msk)
+	for !clks.clk[clkSys].selected.HasBits(0x1) {
 	}
 
-	clks.clk[ClkRef].ctrl.ClearBits(rp.CLOCKS_CLK_REF_CTRL_SRC_Msk)
-	for !clks.clk[ClkRef].selected.HasBits(0x1) {
+	clks.clk[clkRef].ctrl.ClearBits(rp.CLOCKS_CLK_REF_CTRL_SRC_Msk)
+	for !clks.clk[clkRef].selected.HasBits(0x1) {
 	}
 
 	// Configure PLLs
@@ -173,41 +173,41 @@ func (clks *clocksType) init() {
 	pllUSB.init(1, 480*MHz, 5, 2)
 
 	// Configure clocks
-	// ClkRef = xosc (12MHz) / 1 = 12MHz
-	clkref := clks.clock(ClkRef)
-	clkref.configure(rp.CLOCKS_CLK_REF_CTRL_SRC_XOSC_CLKSRC,
+	// clkRef = xosc (12MHz) / 1 = 12MHz
+	cref := clks.clock(clkRef)
+	cref.configure(rp.CLOCKS_CLK_REF_CTRL_SRC_XOSC_CLKSRC,
 		0, // No aux mux
 		12*MHz,
 		12*MHz)
 
-	// ClkSys = pllSys (125MHz) / 1 = 125MHz
-	clksys := clks.clock(ClkSys)
-	clksys.configure(rp.CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX,
+	// clkSys = pllSys (125MHz) / 1 = 125MHz
+	csys := clks.clock(clkSys)
+	csys.configure(rp.CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX,
 		rp.CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_SYS,
 		125*MHz,
 		125*MHz)
 
-	// ClkUSB = pllUSB (48MHz) / 1 = 48MHz
-	clkusb := clks.clock(ClkUSB)
-	clkusb.configure(0, // No GLMUX
+	// clkUSB = pllUSB (48MHz) / 1 = 48MHz
+	cusb := clks.clock(clkUSB)
+	cusb.configure(0, // No GLMUX
 		rp.CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_USB,
 		48*MHz,
 		48*MHz)
 
-	// ClkADC = pllUSB (48MHZ) / 1 = 48MHz
-	clkadc := clks.clock(ClkADC)
-	clkadc.configure(0, // No GLMUX
+	// clkADC = pllUSB (48MHZ) / 1 = 48MHz
+	cadc := clks.clock(clkADC)
+	cadc.configure(0, // No GLMUX
 		rp.CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_USB,
 		48*MHz,
 		48*MHz)
 
 	clks.initRTC()
 
-	// ClkPeri = ClkSys. Used as reference clock for Peripherals.
+	// clkPeri = clkSys. Used as reference clock for Peripherals.
 	// No dividers so just select and enable.
-	// Normally choose ClkSys or ClkUSB.
-	clkperi := clks.clock(ClkPeri)
-	clkperi.configure(0,
+	// Normally choose clkSys or clkUSB.
+	cperi := clks.clock(clkPeri)
+	cperi.configure(0,
 		rp.CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS,
 		125*MHz,
 		125*MHz)