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authorAndrzej Janik <[email protected]>2020-10-01 18:13:09 +0200
committerAndrzej Janik <[email protected]>2020-10-01 18:13:09 +0200
commit96a342e33f221803874ff897f4aa1aa3aae8e71c (patch)
treec8bff9683a1568ef4aaa40c0fbb7e26ccbc91f0b /ptx/src/ptx.lalrpop
parent3e92921275473e3dc028ff5159a17179af6047ba (diff)
downloadZLUDA-96a342e33f221803874ff897f4aa1aa3aae8e71c.tar.gz
ZLUDA-96a342e33f221803874ff897f4aa1aa3aae8e71c.zip
Implement shr
Diffstat (limited to 'ptx/src/ptx.lalrpop')
-rw-r--r--ptx/src/ptx.lalrpop18
1 files changed, 18 insertions, 0 deletions
diff --git a/ptx/src/ptx.lalrpop b/ptx/src/ptx.lalrpop
index ba3fc2b..debdae7 100644
--- a/ptx/src/ptx.lalrpop
+++ b/ptx/src/ptx.lalrpop
@@ -439,6 +439,7 @@ Instruction: ast::Instruction<ast::ParsedArgParams<'input>> = {
InstBra,
InstCvt,
InstShl,
+ InstShr,
InstSt,
InstRet,
InstCvta,
@@ -918,6 +919,23 @@ ShlType: ast::ShlType = {
".b64" => ast::ShlType::B64,
};
+// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shr
+InstShr: ast::Instruction<ast::ParsedArgParams<'input>> = {
+ "shr" <t:ShrType> <a:Arg3> => ast::Instruction::Shr(t, a)
+};
+
+ShrType: ast::ShrType = {
+ ".b16" => ast::ShrType::B16,
+ ".b32" => ast::ShrType::B32,
+ ".b64" => ast::ShrType::B64,
+ ".u16" => ast::ShrType::U16,
+ ".u32" => ast::ShrType::U32,
+ ".u64" => ast::ShrType::U64,
+ ".s16" => ast::ShrType::S16,
+ ".s32" => ast::ShrType::S32,
+ ".s64" => ast::ShrType::S64,
+};
+
// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st
// Warning: NVIDIA documentation is incorrect, you can specify scope only once
InstSt: ast::Instruction<ast::ParsedArgParams<'input>> = {