| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-03-02 | backend/rv64: Implement basic Add32 | Yang Liu | |
| 2024-03-02 | backend/rv64: Implement GetCFlagFromNZCV | Yang Liu | |
| 2024-03-02 | backend/rv64: Implement basic LogicalShiftRight32 | Yang Liu | |
| 2024-03-02 | backend/rv64: Stub all IR instruction implementations | Yang Liu | |
| 2024-03-02 | mcl: Add UNIMPLEMENTED macro | Yang Liu | |
| 2024-03-02 | backend/rv64: Implement A32SetCpsrNZCV | Yang Liu | |
| 2024-03-02 | backend/rv64: Implement GetNZCVFromOp | Yang Liu | |
| 2024-03-02 | backend/rv64: Implement basic Sub32 | Yang Liu | |
| 2024-03-02 | backend/rv64: Implement Identity | Yang Liu | |
| 2024-03-02 | backend/rv64: Initial implementation of terminals | Yang Liu | |
| 2024-03-02 | backend/rv64: Add StackLayout to stack | Yang Liu | |
| 2024-03-02 | backend/rv64: Implement UpdateAllUses | Yang Liu | |
| 2024-03-02 | backend/rv64: Implement AssertNoMoreUses and some minor tweaks | Yang Liu | |
| 2024-03-02 | backend/rv64: Use biscuit LI() | Yang Liu | |
| 2024-03-02 | backend/rv64: Add minimal toy implementation enough to execute LSLS | Yang Liu | |
| 2024-03-02 | backend/rv64: Initial implementation of register allocator | Yang Liu | |
| 2024-03-02 | backend/rv64: Adjust how relocations are stored | Yang Liu | |
| 2024-03-02 | backend/rv64: Rework on pointer types | Yang Liu | |
| 2024-03-02 | backend/rv64: Add a dummy code generation | Yang Liu | |
| 2024-03-02 | backend/rv64: Add biscuit as the assembler | Yang Liu | |
| 2024-03-02 | backend/rv64: Add initial RISC-V framework | Yang Liu | |
| RISC-V target is now compilable. | |||
| 2024-03-02 | github: Add basic RISC-V CI | Yang Liu | |
| 2024-03-02 | externals: Add biscuit | Merry | |
| Merge commit 'e4a733d5b2e02e7095847892f29ed8288d55d91e' as 'externals/biscuit' | |||
| 2024-03-02 | Squashed 'externals/biscuit/' content from commit 1d53c9e6 | Merry | |
| git-subtree-dir: externals/biscuit git-subtree-split: 1d53c9e6cfe56544982200a5bac15a5de064936b | |||
| 2024-03-02 | dynarmic: 6.7.0 | Merry | |
| 2024-03-02 | Change Config to make fastmem_pointer of zero valid. | Ash | |
| This changes Dynarmic::A32/A64::Config to store fastmem_pointer in a std::optional<uintptr_t>, allowing the user to pass a zero base address for the guest memory, which can be used to effectively implement a shared address space between the host and the guest. | |||
| 2024-02-24 | emit_x64_vector: Implement AVX2 AVShift64 | zmt00 | |
| 2024-02-24 | emit_x64_vector: Refactor AVX2 AVShift32, LVShift{32,64} | zmt00 | |
| 2024-02-24 | tests/A64: Update {S,U}SHL tests | zmt00 | |
| Converted tests to use oaknut, and added some extra test cases. SSHL's additional tests are targetd to make sure that the sign of the lowest byte is used to determine shift direction, not the entire element. USHL targets this as well as just having more negative (right shift) cases in general. | |||
| 2024-02-20 | emit_x64_vector: Implement AVX2 UnsignedRoundingShiftLeft{32,64} | zmt00 | |
| 2024-02-20 | tests/A64: Add URSHL tests | zmt00 | |
| 2024-02-17 | emit_x64_vector: Refactor pre-SSE4.1 min/max instruction replacements | zmt00 | |
| 2024-02-17 | tests/A64: Add non-paired min/max integer tests | zmt00 | |
| 2024-02-13 | emit_x64_vector: Optimize VectorSignedSaturatedAbs | zmt00 | |
| 2024-02-13 | tests/A64: Add SQABS tests | zmt00 | |
| 2024-02-13 | backend/arm64: A64: Implement DumpDisassembly | Merry | |
| 2024-02-13 | emit_arm64_a64: Take into account currently loaded FPSR | Merry | |
| Previously we just retrieved the last stored FPSR and used that when the guest asks for the current FPSR. This is incorrect behaviour. We failed to take into account the current state of the host FPSR. Here we take this into account. This bug was discovered via #795. | |||
| 2024-02-10 | dynarmic: 6.6.3 | Merry | |
| 2024-02-10 | backend/x64: Reduce races on invalidation requests in interface | Merry | |
| This situation occurs when RequestCacheInvalidation is called from multiple threads. This results in unusual issues around memory allocation which arise from concurrent access to invalid_cache_ranges. There are several reasons for this: 1. No locking around the invalidation queue. 2. is_executing is not multithread safe. So here we reduce any cache clear or any invalidation to raise a CacheInvalidation halt, which we execute immediately before or immediately after Run() instead. | |||
| 2024-02-10 | tests/A64: Add negative-shift elements to `USHL` | Wunkolo | |
| 2024-02-10 | emit_x64_vector: AVX512+GNFI implementation of EmitVectorLogicalVShift8 | Wunkolo | |
| 2024-02-10 | tests/A64: Convert recent tests to oaknut | zmt00 | |
| 2024-02-10 | ir: Implement FPMulSub | zmt00 | |
| 2024-02-06 | tests/A64: Use oaknut for CLZ assembly | Wunkolo | |
| 2024-02-06 | emit_x64_vector: GNFI implementation of EmitVectorCountLeadingZeros8 | Wunkolo | |
| 2024-02-06 | tests/A64: Add CLZ vector unit-tests | Wunkolo | |
| 2024-01-31 | emit_x64_data_processing: Exclude edge case from lea path in EmitSub | Merry | |
| -0xffff'ffff'8000'0000 = 0x0000'0000'8000'0000 which is not a representable displacement | |||
| 2024-01-30 | constant_propagation_pass: x + 0 == x | Merry | |
| 2024-01-30 | emit_x64_data_processing: Emit lea where possible in EmitAdd and EmitSub | Merry | |
| 2024-01-30 | Avoid emplace. | Merry | |
 |
index : dynarmic | |
| A dynamic recompiler for ARM. | merryhime |
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